We'll use the sc.q instruction for some 16-byte atomic operations, but
it's only added in LoongArch 1.1 evolution so we need to gate it with
an option.
gcc/ChangeLog:
* config/loongarch/genopts/isa-evolution.in (scq): New evolution
feature.
* config/loongarch/loongarch-evolution.cc: Regenerate.
* config/loongarch/loongarch-evolution.h: Regenerate.
* config/loongarch/loongarch-str.h: Regenerate.
* config/loongarch/loongarch.opt: Regenerate.
* config/loongarch/loongarch-def.cc: Make -mscq the default for
-march=la664 and -march=la64v1.1.
* doc/invoke.texi (LoongArch Options): Document -m[no-]scq.
---
gcc/config/loongarch/genopts/isa-evolution.in | 1 +
gcc/config/loongarch/loongarch-def.cc | 4 ++--
gcc/config/loongarch/loongarch-evolution.cc | 4 ++++
gcc/config/loongarch/loongarch-evolution.h | 8 ++++++--
gcc/config/loongarch/loongarch-str.h | 1 +
gcc/config/loongarch/loongarch.opt | 4 ++++
gcc/doc/invoke.texi | 11 ++++++++++-
7 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/gcc/config/loongarch/genopts/isa-evolution.in
b/gcc/config/loongarch/genopts/isa-evolution.in
index 50f72d5a0bc..836d93a0038 100644
--- a/gcc/config/loongarch/genopts/isa-evolution.in
+++ b/gcc/config/loongarch/genopts/isa-evolution.in
@@ -2,4 +2,5 @@
2 26 div32 1.1 Support div.w[u] and mod.w[u]
instructions with inputs not sign-extended.
2 27 lam-bh 1.1 Support am{swap/add}[_db].{b/h}
instructions.
2 28 lamcas 1.1 Support amcas[_db].{b/h/w/d}
instructions.
+2 30 scq 1.1 Support sc.q instruction.
3 23 ld-seq-sa 1.1 Do not need load-load barriers
(dbar 0x700).
diff --git a/gcc/config/loongarch/loongarch-def.cc
b/gcc/config/loongarch/loongarch-def.cc
index 5f235a04ef2..b19720ee066 100644
--- a/gcc/config/loongarch/loongarch-def.cc
+++ b/gcc/config/loongarch/loongarch-def.cc
@@ -72,7 +72,7 @@ array_arch<loongarch_isa> loongarch_cpu_default_isa =
.simd_ (ISA_EXT_SIMD_LASX)
.evolution_ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA
| OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS
- | OPTION_MASK_ISA_FRECIPE))
+ | OPTION_MASK_ISA_FRECIPE | OPTION_MASK_ISA_SCQ))
.set (ARCH_LA64V1_0,
loongarch_isa ()
.base_ (ISA_BASE_LA64)
@@ -86,7 +86,7 @@ array_arch<loongarch_isa> loongarch_cpu_default_isa =
.simd_ (ISA_EXT_SIMD_LSX)
.evolution_ (OPTION_MASK_ISA_DIV32 | OPTION_MASK_ISA_LD_SEQ_SA
| OPTION_MASK_ISA_LAM_BH | OPTION_MASK_ISA_LAMCAS
- | OPTION_MASK_ISA_FRECIPE));
+ | OPTION_MASK_ISA_FRECIPE | OPTION_MASK_ISA_SCQ));
static inline loongarch_cache la464_cache ()
diff --git a/gcc/config/loongarch/loongarch-evolution.cc
b/gcc/config/loongarch/loongarch-evolution.cc
index de68624f949..a92a6455df6 100644
--- a/gcc/config/loongarch/loongarch-evolution.cc
+++ b/gcc/config/loongarch/loongarch-evolution.cc
@@ -32,6 +32,7 @@ int la_evo_feature_masks[] = {
OPTION_MASK_ISA_DIV32,
OPTION_MASK_ISA_LAM_BH,
OPTION_MASK_ISA_LAMCAS,
+ OPTION_MASK_ISA_SCQ,
OPTION_MASK_ISA_LD_SEQ_SA,
};
@@ -40,6 +41,7 @@ const char* la_evo_macro_name[] = {
"__loongarch_div32",
"__loongarch_lam_bh",
"__loongarch_lamcas",
+ "__loongarch_scq",
"__loongarch_ld_seq_sa",
};
@@ -48,6 +50,7 @@ int la_evo_version_major[] = {
1, /* DIV32 */
1, /* LAM_BH */
1, /* LAMCAS */
+ 1, /* SCQ */
1, /* LD_SEQ_SA */
};
@@ -56,5 +59,6 @@ int la_evo_version_minor[] = {
1, /* DIV32 */
1, /* LAM_BH */
1, /* LAMCAS */
+ 1, /* SCQ */
1, /* LD_SEQ_SA */
};
diff --git a/gcc/config/loongarch/loongarch-evolution.h
b/gcc/config/loongarch/loongarch-evolution.h
index 5f908394c22..7fb7b0d3d86 100644
--- a/gcc/config/loongarch/loongarch-evolution.h
+++ b/gcc/config/loongarch/loongarch-evolution.h
@@ -36,6 +36,7 @@ static constexpr struct {
{ 2, 1u << 26, OPTION_MASK_ISA_DIV32 },
{ 2, 1u << 27, OPTION_MASK_ISA_LAM_BH },
{ 2, 1u << 28, OPTION_MASK_ISA_LAMCAS },
+ { 2, 1u << 30, OPTION_MASK_ISA_SCQ },
{ 3, 1u << 23, OPTION_MASK_ISA_LD_SEQ_SA },
};
@@ -58,8 +59,9 @@ enum {
EVO_DIV32 = 1,
EVO_LAM_BH = 2,
EVO_LAMCAS = 3,
- EVO_LD_SEQ_SA = 4,
- N_EVO_FEATURES = 5
+ EVO_SCQ = 4,
+ EVO_LD_SEQ_SA = 5,
+ N_EVO_FEATURES = 6
};
/* Condition macros */
@@ -71,6 +73,8 @@ enum {
(la_target.isa.evolution & OPTION_MASK_ISA_LAM_BH)
#define ISA_HAS_LAMCAS \
(la_target.isa.evolution & OPTION_MASK_ISA_LAMCAS)
+#define ISA_HAS_SCQ \
+ (la_target.isa.evolution & OPTION_MASK_ISA_SCQ)
#define ISA_HAS_LD_SEQ_SA \
(la_target.isa.evolution & OPTION_MASK_ISA_LD_SEQ_SA)
diff --git a/gcc/config/loongarch/loongarch-str.h
b/gcc/config/loongarch/loongarch-str.h
index 1546ea39443..583cce8643e 100644
--- a/gcc/config/loongarch/loongarch-str.h
+++ b/gcc/config/loongarch/loongarch-str.h
@@ -70,6 +70,7 @@ along with GCC; see the file COPYING3. If not see
#define OPTSTR_DIV32 "div32"
#define OPTSTR_LAM_BH "lam-bh"
#define OPTSTR_LAMCAS "lamcas"
+#define OPTSTR_SCQ "scq"
#define OPTSTR_LD_SEQ_SA "ld-seq-sa"
#endif /* LOONGARCH_STR_H */
diff --git a/gcc/config/loongarch/loongarch.opt
b/gcc/config/loongarch/loongarch.opt
index 4d85cf5a804..fbe61c0bf7c 100644
--- a/gcc/config/loongarch/loongarch.opt
+++ b/gcc/config/loongarch/loongarch.opt
@@ -334,6 +334,10 @@ mlamcas
Target Mask(ISA_LAMCAS) Var(la_isa_evolution)
Support amcas[_db].{b/h/w/d} instructions.
+mscq
+Target Mask(ISA_SCQ) Var(la_isa_evolution)
+Support sc.q instruction.
+
mld-seq-sa
Target Mask(ISA_LD_SEQ_SA) Var(la_isa_evolution)
Do not need load-load barriers (dbar 0x700).
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 6f8bf392386..bef30e32384 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1089,7 +1089,8 @@ Objective-C and Objective-C++ Dialects}.
-mcmodel=@var{code-model} -mrelax -mpass-mrelax-to-as
-mrecip -mrecip=@var{opt} -mfrecipe -mno-frecipe -mdiv32 -mno-div32
-mlam-bh -mno-lam-bh -mlamcas -mno-lamcas -mld-seq-sa -mno-ld-seq-sa
--mtls-dialect=@var{opt} -mannotate-tablejump -mno-annotate-tablejump}
+-mscq -mno-scq -mtls-dialect=@var{opt}
+-mannotate-tablejump -mno-annotate-tablejump}
@emph{M32C Options} (@ref{M32C Options})
@gccoptlist{-mcpu=@var{cpu} -msim -memregs=@var{number}}
@@ -27917,6 +27918,14 @@ Whether a load-load barrier (@code{dbar 0x700}) is
needed. When build with
@option{-march=la664}, it is enabled by default. The default is
@option{-mno-ld-seq-sa}, the load-load barrier is needed.
+@opindex mscq
+@opindex mno-scq
+@item -mscq
+@item -mno-scq
+Use (do not use) the 16-byte conditional store instruction @code{sc.q}.
+The default is @option{-mscq} if the machine type specified with
+@option{-march=} supports this instruction, @option{-mno-scq} otherwise.
+
@opindex mtls-dialect
@item -mtls-dialect=@var{opt}
This option controls which tls dialect may be used for general dynamic and
--
2.48.1
