gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/xtheadvector/pr114194.c: Adjust correctly.
* gcc.target/riscv/rvv/xtheadvector/prefix.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c: Likewise.
* gcc.target/riscv/rvv/xtheadvector/xtheadvector.exp: New test.
---
.../riscv/rvv/xtheadvector/pr114194.c | 32 +++++++--------
.../riscv/rvv/xtheadvector/prefix.c | 2 +-
.../riscv/rvv/xtheadvector/vlb-vsb.c | 17 ++++----
.../riscv/rvv/xtheadvector/vlbu-vsb.c | 17 ++++----
.../riscv/rvv/xtheadvector/vlh-vsh.c | 17 ++++----
.../riscv/rvv/xtheadvector/vlhu-vsh.c | 17 ++++----
.../riscv/rvv/xtheadvector/vlw-vsw.c | 17 ++++----
.../riscv/rvv/xtheadvector/vlwu-vsw.c | 17 ++++----
.../riscv/rvv/xtheadvector/xtheadvector.exp | 40 +++++++++++++++++++
9 files changed, 117 insertions(+), 59 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/xtheadvector.exp
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
index a82e2d3fbfe6..5c9777b071b5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/pr114194.c
@@ -1,11 +1,11 @@
/* { dg-do compile { target { ! riscv_abi_e } } } */
-/* { dg-options "-march=rv32gc_xtheadvector" { target { rv32 } } } */
-/* { dg-options "-march=rv64gc_xtheadvector" { target { rv64 } } } */
+/* { dg-options "-march=rv32gc_xtheadvector -O2" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadvector -O2" { target { rv64 } } } */
/* { dg-final { check-function-bodies "**" "" } } */
/*
** foo0_1:
-** sb\tzero,0([a-x0-9]+)
+** sb\tzero,0\([a-x0-9]+\)
** ret
*/
void foo0_1 (void *p)
@@ -15,13 +15,13 @@ void foo0_1 (void *p)
/*
** foo0_7:
-** sb\tzero,0([a-x0-9]+)
-** sb\tzero,1([a-x0-9]+)
-** sb\tzero,2([a-x0-9]+)
-** sb\tzero,3([a-x0-9]+)
-** sb\tzero,4([a-x0-9]+)
-** sb\tzero,5([a-x0-9]+)
-** sb\tzero,6([a-x0-9]+)
+** sb\tzero,0\([a-x0-9]+\)
+** sb\tzero,1\([a-x0-9]+\)
+** sb\tzero,2\([a-x0-9]+\)
+** sb\tzero,3\([a-x0-9]+\)
+** sb\tzero,4\([a-x0-9]+\)
+** sb\tzero,5\([a-x0-9]+\)
+** sb\tzero,6\([a-x0-9]+\)
** ret
*/
void foo0_7 (void *p)
@@ -32,7 +32,7 @@ void foo0_7 (void *p)
/*
** foo1_1:
** li\t[a-x0-9]+,1
-** sb\t[a-x0-9]+,0([a-x0-9]+)
+** sb\t[a-x0-9]+,0\([a-x0-9]+\)
** ret
*/
void foo1_1 (void *p)
@@ -43,11 +43,11 @@ void foo1_1 (void *p)
/*
** foo1_5:
** li\t[a-x0-9]+,1
-** sb\t[a-x0-9]+,0([a-x0-9]+)
-** sb\t[a-x0-9]+,1([a-x0-9]+)
-** sb\t[a-x0-9]+,2([a-x0-9]+)
-** sb\t[a-x0-9]+,3([a-x0-9]+)
-** sb\t[a-x0-9]+,4([a-x0-9]+)
+** sb\t[a-x0-9]+,0\([a-x0-9]+\)
+** sb\t[a-x0-9]+,1\([a-x0-9]+\)
+** sb\t[a-x0-9]+,2\([a-x0-9]+\)
+** sb\t[a-x0-9]+,3\([a-x0-9]+\)
+** sb\t[a-x0-9]+,4\([a-x0-9]+\)
** ret
*/
void foo1_5 (void *p)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
index eee727ef6b42..0a18e697830c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c
@@ -9,4 +9,4 @@ prefix (vint32m1_t vx, vint32m1_t vy, size_t vl)
return __riscv_vadd_vv_i32m1 (vx, vy, vl);
}
-/* { dg-final { scan-assembler {\mth\.v\M} } } */
+/* { dg-final { scan-assembler {\mth\.vadd\.vv\M} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
index 3c12c1245974..16073ccb2366 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlb-vsb.c
@@ -5,7 +5,8 @@
/*
** f1:
-** th.vsetivli\tzero,4,e32,m1,tu,ma
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlb\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vlb\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
@@ -24,9 +25,10 @@ void f1 (void * in, void *out)
/*
** f2:
-** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** th.vsetivli\tzero,4,e32,m1,ta,ma
+** th.vsetvli\tzero,zero,e8,m1
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlb.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
** th.vadd\.vv\tv[1-9][0-9]?,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t
@@ -46,9 +48,10 @@ void f2 (void * in, void *out)
/*
** f3:
-** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** th.vsetivli\tzero,4,e32,m1,tu,mu
+** th.vsetvli\tzero,zero,e8,m1
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlb\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vlb.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** th.vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
index 30bef369375f..f60f125c0e56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlbu-vsb.c
@@ -5,7 +5,8 @@
/*
** f1:
-** th.vsetivli\tzero,4,e32,m1,tu,ma
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlbu\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vlbu\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +25,10 @@ void f1 (void * in, void *out, uint32_t x)
/*
** f2:
-** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** th.vsetivli\tzero,4,e32,m1,ta,ma
+** th.vsetvli\tzero,zero,e8,m1
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlbu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +48,10 @@ void f2 (void * in, void *out, uint32_t x)
/*
** f3:
-** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** th.vsetivli\tzero,4,e32,m1,tu,mu
+** th.vsetvli\tzero,zero,e8,m1
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlbu\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vlbu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
index 3c8b5ccc16ba..ec1a18f33cd3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlh-vsh.c
@@ -5,7 +5,8 @@
/*
** f1:
-** th.vsetivli\tzero,4,e32,m1,tu,ma
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlh\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vlh\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +25,10 @@ void f1 (void * in, void *out, int32_t x)
/*
** f2:
-** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** th.vsetivli\tzero,4,e32,m1,ta,ma
+** th.vsetvli\tzero,zero,e8,m1
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlh.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +48,10 @@ void f2 (void * in, void *out, int32_t x)
/*
** f3:
-** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** th.vsetivli\tzero,4,e32,m1,tu,mu
+** th.vsetvli\tzero,zero,e8,m1
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlh\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vlh.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
index b7c00404f181..6cdd2dd8eb0c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlhu-vsh.c
@@ -5,7 +5,8 @@
/*
** f1:
-** th.vsetivli\tzero,4,e32,m1,tu,ma
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlhu\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vlhu\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +25,10 @@ void f1 (void * in, void *out, uint32_t x)
/*
** f2:
-** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** th.vsetivli\tzero,4,e32,m1,ta,ma
+** th.vsetvli\tzero,zero,e8,m1
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlhu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +48,10 @@ void f2 (void * in, void *out, uint32_t x)
/*
** f3:
-** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** th.vsetivli\tzero,4,e32,m1,tu,mu
+** th.vsetvli\tzero,zero,e8,m1
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlhu\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vlhu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
index 17a53012acf7..74a2369f1353 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlw-vsw.c
@@ -5,7 +5,8 @@
/*
** f1:
-** th.vsetivli\tzero,4,e32,m1,tu,ma
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlw\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vlw\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
@@ -24,9 +25,10 @@ void f1 (void * in, void *out, int32_t x)
/*
** f2:
-** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** th.vsetivli\tzero,4,e32,m1,ta,ma
+** th.vsetvli\tzero,zero,e8,m1
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlw.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
** th.vadd\.vx\tv[1-9][0-9]?,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t
@@ -46,9 +48,10 @@ void f2 (void * in, void *out, int32_t x)
/*
** f3:
-** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** th.vsetivli\tzero,4,e32,m1,tu,mu
+** th.vsetvli\tzero,zero,e8,m1
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlw\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vlw.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** th.vadd\.vx\tv[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
index b187cfc852b9..0ddc3e8808b0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/vlwu-vsw.c
@@ -5,7 +5,8 @@
/*
** f1:
-** th.vsetivli\tzero,4,e32,m1,tu,ma
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlwu\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vlwu\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
@@ -24,9 +25,10 @@ void f1 (void * in, void *out, uint32_t x)
/*
** f2:
-** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** th.vsetivli\tzero,4,e32,m1,ta,ma
+** th.vsetvli\tzero,zero,e8,m1
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlwu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
** th.vadd\.vi\tv[1-9][0-9]?,\s*v[0-9]+,\s*-16,\s*v0.t
@@ -46,9 +48,10 @@ void f2 (void * in, void *out, uint32_t x)
/*
** f3:
-** th.vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma
-** th.vlm.v\tv[0-9]+,0\([a-x0-9]+\)
-** th.vsetivli\tzero,4,e32,m1,tu,mu
+** th.vsetvli\tzero,zero,e8,m1
+** th.vle.v\tv[0-9]+,0\([a-x0-9]+\)
+** li\t[a-x0-9]+,4
+** th.vsetvli\tzero,[a-x0-9]+,e32,m1
** th.vlwu\.v\tv[0-9]+,0\([a-x0-9]+\)
** th.vlwu.v\tv[0-9]+,0\([a-x0-9]+\),v0.t
** th.vadd\.vi\tv[0-9]+,\s*v[0-9]+,\s*-16
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/xtheadvector.exp
b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/xtheadvector.exp
new file mode 100644
index 000000000000..c3f30b939bba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/xtheadvector.exp
@@ -0,0 +1,40 @@
+# Copyright (C) 2022-2025 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with GCC; see the file COPYING3. If not see
+# <http://www.gnu.org/licenses/>.
+
+# GCC testsuite that uses the `dg.exp' driver.
+
+# Exit immediately if this isn't a RISC-V target.
+if ![istarget riscv*-*-*] then {
+ return
+}
+
+# Load support procs.
+load_lib gcc-dg.exp
+
+# If a testcase doesn't have special options, use these.
+global DEFAULT_CFLAGS
+if ![info exists DEFAULT_CFLAGS] then {
+ set DEFAULT_CFLAGS " -ansi -pedantic-errors"
+}
+
+# Initialize `dg'.
+dg-init
+
+# Main loop.
+dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] "" ""
+
+# All done.
+dg-finish
--
2.25.1
