On 12/11/24 3:40 AM, Oliver Kozul wrote:
The patch optimizes code generation for comparisons of the form
X & C1 == C2. When the bitwise AND mask could fit in a 12-bit immediate
operand of RISC-V "andi" instruction with help of right shifting.
For example, C1 = 0x55500000 and C2 = 0x14500000.
These numbers can be stored using 12 bits, which is advantageous in RISC-V,
since instructions such as ANDI exist. By shifting all used values
by 20 bits to the right, we can make use of the “and immediate” instruction,
thus improving performance.
2024-12-11 Oliver Kozul <oliver.ko...@rt-rk.com>
PR target/114087
gcc/ChangeLog:
* config/riscv/riscv.md (*lui_constraint<ANYI:mode>_lshiftrt): New
pattern.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/pr114087-2.c: New test.
As Oliver and I have discussed privately, he thinks this may be missing
a final shift, similar to another related patch. That is likely the
cause of the pre-commit test failures:
https://github.com/ewlu/gcc-precommit-ci/issues/2728#issuecomment-2535517333
I'm going to assume Oliver will update the patch or drop it if it's not
profitable after fixing the missing shift.
Oliver -- this case may also be worth looking at in the gimple or
gimple->rtl phases as well since the trailing shift can be eliminated
when the result is used exclusively in an equality test and that's
easier to see in gimple or at the gimple->rtl phase.
jeff
