From: Pan Li <pan2...@intel.com>
Some saturation related alu testcases missed additional option
for expand check, which result in some UNRESOLVED issues. This
patch would like to fix it by adding the option back as other
testcases.
The below test are passed for this patch.
* The rv64gcv fully regression test.
It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c: Add
compile option for expanding check.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c: Ditto.
* gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c: Ditto.
* gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c: Ditto.
Signed-off-by: Pan Li <pan2...@intel.com>
---
.../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c | 1 +
.../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c | 1 +
.../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c | 1 +
.../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c | 1 +
.../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c | 1 +
.../gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c | 1 +
.../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c | 1 +
.../gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c | 1 +
8 files changed, 8 insertions(+)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
index 236fe68123f..1320b05e76c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-13.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
index 2eda4197abb..e71758d9c4e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-15.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
index ae97fece59b..1626e857d28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-22.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
index f0c5289764f..8792bb6112b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add-29.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
index 7cde4c9d378..4a93c7f89cb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-15.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c
index 341226838a3..bc6d441759f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/binop/vec_sat_u_add_imm-7.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
index 17e176b87db..d2239d3e42c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-11.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
index 1ebf5c88d3a..9c671cb897b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/vec_sat_u_trunc-12.c
@@ -1,4 +1,5 @@
/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize
-fdump-rtl-expand-details" } */
#include "../vec_sat_arith.h"
--
2.43.0
