On Tue, Sep 17, 2024 at 02:33:09AM -0500, Segher Boessenkool wrote:
> Hi!
>
> On Mon, Sep 16, 2024 at 11:40:45PM -0400, Michael Meissner wrote:
> > With this patch, GCC now realizes that the vector shift instructions will
> > look
> > at the bottom 6 bits for the shift count, and it can use either a VSPLTISW
> > or
> > XXSPLTIB instruction to load the shift count.
>
> Do we do something like this for integer shift instructions already?
We didn't previously, so shifts greater than 15 required 3 instructions
(because we needed 2 instructions to load and splat the value since we couldn't
use VSPLTIS{B,H,W}. This patch fixes those shifts as well.
I.e. for:
typedef vector int vi32_t;
vi32_t
shiftra_test32_29 (vi32_t a)
{
vui32_t x = {29, 29, 29, 29};
return (vi32_t) vec_vsraw (a, x);
}
Previously we generated:
xxspltib 32,29
vextsb2w 0,0
vsraw 2,2,0
blr
Now we generate:
xxspltib 32,29
vsraw 2,2,0
blr
> > + operands[4] = ((GET_CODE (operands[2]) == CONST_VECTOR)
> > + ? CONST_VECTOR_ELT (operands[2], 0)
> > + : XEXP (operands[2], 0));
>
> Useless parens are useless, please lose them?
Done.
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/powerpc/pr89213.c
> > @@ -0,0 +1,106 @@
> > +/* { dg-do compile { target { lp64 } } } */
>
> Why only on 64-bit systems? Does it fail with -m32? Why / how?
>
> With that, okay for trunk. Thanks!
After testing, it works on 32-bit systems as well, and I removed the 64-bit
target requirement.
I have committed the patch with the 2 changes (lose the extra parenthesis and
allow the test on 32-bit).
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: [email protected]
