> -----Original Message-----
> From: Kyrylo Tkachov <ktkac...@nvidia.com>
> Sent: Friday, September 6, 2024 2:15 PM
> To: Tamar Christina <tamar.christ...@arm.com>
> Cc: GCC Patches <gcc-patches@gcc.gnu.org>; nd <n...@arm.com>; Richard Biener
> <rguent...@suse.de>; j...@ventanamicro.com
> Subject: Re: [PATCH]middle-end: check that the lhs of a COND_EXPR is an
> SSA_NAME in cond_store recognition [PR116628]
>
> Hi Tamar,
>
>
> > On 6 Sep 2024, at 14:56, Tamar Christina <tamar.christ...@arm.com> wrote:
> >
> > External email: Use caution opening links or attachments
> >
> >
> > Hi All,
> >
> > Because the vect_recog_bool_pattern can at the moment still transition
> > out of GIMPLE and back into GENERIC the vect_recog_cond_store_pattern can
> > end up using an expression as a mask rather than an SSA_NAME.
> >
> > This adds an explicit check that we have a mask and not an expression.
> >
> > Bootstrapped Regtested on aarch64-none-linux-gnu and no issues.
> >
> > Ok for master?
> >
> > Thanks,
> > Tamar
> >
> > gcc/ChangeLog:
> >
> > PR tree-optimization/116628
> > * tree-vect-patterns.cc (vect_recog_cond_store_pattern): Add SSA_NAME
> > check on expression.
> >
> > gcc/testsuite/ChangeLog:
> >
> > PR tree-optimization/116628
> > * gcc.dg/vect/pr116628.c: New test.
> >
> > ---
> > diff --git a/gcc/testsuite/gcc.dg/vect/pr116628.c
> b/gcc/testsuite/gcc.dg/vect/pr116628.c
> > new file mode 100644
> > index
> 0000000000000000000000000000000000000000..4068c657ac5570b10f2dca
> 4be5109abbaf574f55
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.dg/vect/pr116628.c
> > @@ -0,0 +1,14 @@
> > +/* { dg-do compile } */
> > +/* { dg-require-effective-target vect_float } */
> > +/* { dg-require-effective-target vect_masked_store } */
> > +/* { dg-additional-options "-Ofast -march=armv9-a" { target aarch64-*-* }
> > } */
>
> FWIW the ICE in the PR doesn’t trigger for me with -march=armv9-a. I think
> something in the heuristics for -mcpu=neoverse-v2 is needed.
Hmm so it does generate the wrong pattern, but only for VNx2QI and due to
costing
It's not chosen. Looks like any VL128 sve picks the wrong one.
Ok I'll just update the test.
Thanks,
Tamar
> Thanks,
> Kyrill
>
> > +
> > +typedef float c;
> > +c a[2000], b[0];
> > +void d() {
> > + for (int e = 0; e < 2000; e++)
> > + if (b[e])
> > + a[e] = b[e];
> > +}
> > +
> > +/* { dg-final { scan-tree-dump "LOOP VECTORIZED" "vect" } } */
> > diff --git a/gcc/tree-vect-patterns.cc b/gcc/tree-vect-patterns.cc
> > index
> f7c3c623ea46ea09f4f86139d2a92bb6363aee3c..3a0d4cb7092cb59fe8b8664b6
> 82ade73ab5e9645 100644
> > --- a/gcc/tree-vect-patterns.cc
> > +++ b/gcc/tree-vect-patterns.cc
> > @@ -6685,6 +6685,9 @@ vect_recog_cond_store_pattern (vec_info *vinfo,
> > /* Check if the else value matches the original loaded one. */
> > bool invert = false;
> > tree cmp_ls = gimple_arg (cond_stmt, 0);
> > + if (TREE_CODE (cmp_ls) != SSA_NAME)
> > + return NULL;
> > +
> > tree cond_arg1 = gimple_arg (cond_stmt, 1);
> > tree cond_arg2 = gimple_arg (cond_stmt, 2);
> >
> >
> >
> >
> >
> > --
> > <rb18763.patch>
