Hello,
On Sun, 25 Aug 2024, Jeff Law wrote:
> > 550: [--sp] = 0 sp_off = 0 {pushexthisi_const}
> > 551: [--sp] = 37 sp_off = -4 {pushexthisi_const}
> > 552: [--sp] = r37 sp_off = -8 {movsi_m68k2}
> > 554: [--sp] = r116 - r37 sp_off = -12 {subsi3}
> > 556: call sp_off = -16
> >
> > insn 554 doesn't match its constraints and needs some reloads:
>
> I think you're right in that the current code isn't correct, but the
> natural question is how in the world has this worked to-date. Though I
> guess targets which push arguments are a dying breed (though I would
> have expected i386 to have tripped over this at some point).
Yeah, I wondered as well. For things to go wrong some instructions that
contain pre/post-inc/dec of the stack pointer need to have reloads in such
a way that the actual SP-change sideeffect moves to a different
instruction. In this case it was:
554: [--sp] = r116 - r37
-->
996: r262 = r116
554: r262 = r262 - r37
997: [--sp] = r262
And for this to happen the targets needs to have instructions that have
SP-change sideeffect _and_ accept complicated expressions _and_ constrain
the operand containing the side-effect in some way to the operands of
these expressions. (In this case: the subsi3 accepts a generic
mem-operand destination, which includes pre-increment, and two generic
register input operands; but constrains it such that the dest must be same
as op0 of the minus).
I guess that LRA targets until now, when they have SP-change (e.g. x86
push/pop) are simple enough that the SP-change doesn't need reload. E.g.
the push on i386 only accepts a simple register or memory as input, and
doesn't otherwise tie the SP-memory operands to the input:
[--sp] = op0 # a simple push of simple general_operand op0
If any reloads are necessary for some reason then it will be on op0 which
most likely will simply be a force_reg:
regT = op0
[--sp] = regT
The identity of the instruction that does the SP-change doesn't change.
setup_sp_offset will only be called on the new regT setter which doesn't
contain any interesting effects on SP whatsoever, and the sp_offset value
of the push will remain correct for it.
But if there are output reloads that contain the [--sp] things will go
wrong, as here. Typical RISC ISAs, even if they have SP-changes will have
them in their load/store insns, in which any reloads are similar to the
x86 case: the side-effect will remain on the original instruction and
everything will work.
> OK. Though I fear there may be fallout on this one...
Me as well, but I can have hope, can I? :-)
Ciao,
Michael.
