On Mon, Aug 5, 2024 at 8:49 AM Kyrylo Tkachov <ktkac...@nvidia.com> wrote: > > Hi all, > > The code in get_reassociation_width that forms FMAs aggressively when > they are fully pipelined expects the FMUL reassociation width in the > target to be less than for FMAs. This doesn't hold for all target > tunings. > > This code shouldn't ICE, just avoid forming these FMAs here. > This patch does that. > > The test case uses -mcpu=neoverse-n3 tuning because it uses the width of 6 > for the fp reassociation cost. The test case in the PR uses neoverse-v2 but I > intend to change the reassociation cost for neoverse-v2 in a future patch > that would not trigger this ICE. > > Bootstrapped and tested on aarch64-none-linux-gnu. > Ok for trunk?
OK for trunk and affected branches. Richard. > Thanks, > Kyrill > > Signed-off-by: Kyrylo Tkachov <ktkac...@nvidia.com> > > PR tree-optimization/116139 > > gcc/ChangeLog: > > * tree-ssa-reassoc.cc (get_reassociation_width): Move width_mult > <= width comparison to if condition rather than assert. > > gcc/testsuite/ChangeLog: > > * gcc.target/aarch64/pr116139.c: New test. > --- >
