On 7/17/24 4:55 AM, demin.han wrote:
There are still some cases which can't utilize vx or vf for autovec
comparison after last_combine pass.
1. integer comparison when imm isn't in range of [-16, 15]
2. float imm is 0.0
3. DI or DF mode under RV32
This patch fix above mentioned issues.
Tested on RV32 and RV64.
gcc/ChangeLog:
* config/riscv/autovec.md: register_operand to nonmemory_operand
* config/riscv/riscv-v.cc (get_cmp_insn_code): Select code according
* to scalar_p
(expand_vec_cmp): Generate scalar_p and transform op1
* config/riscv/riscv.cc (riscv_const_insns): Add !FLOAT_MODE_P
* constrain
* config/riscv/vector.md: Add !FLOAT_MODE_P constrain
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/binop/vadd-rv32gcv-nofm.c: Fix test
* gcc.target/riscv/rvv/autovec/binop/vdiv-rv32gcv-nofm.c: Ditto
* gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv-nofm.c: Ditto
* gcc.target/riscv/rvv/autovec/binop/vsub-rv32gcv-nofm.c: Ditto
* gcc.target/riscv/rvv/autovec/cmp/vcond-1.c: Fix and add test
* gcc.target/riscv/rvv/autovec/cond/cond_copysign-rv32gcv.c: Fix
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-1.c: Fix test
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-2.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-3.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fadd-4.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-1.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-3.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-4.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-5.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fma_fnma-6.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-1.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-2.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-3.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmax-4.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-1.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-2.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-3.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmin-4.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-1.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-3.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-4.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-5.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fms_fnms-6.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-1.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-2.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-3.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-4.c: Ditto
* gcc.target/riscv/rvv/autovec/cond/cond_fmul-5.c: Ditto
Signed-off-by: demin.han <demin....@starfivetech.com>
---
gcc/config/riscv/autovec.md | 2 +-
gcc/config/riscv/riscv-v.cc | 72 ++++++++++++-------
gcc/config/riscv/riscv.cc | 2 +-
gcc/config/riscv/vector.md | 3 +-
.../rvv/autovec/binop/vadd-rv32gcv-nofm.c | 4 +-
.../rvv/autovec/binop/vdiv-rv32gcv-nofm.c | 4 +-
.../rvv/autovec/binop/vmul-rv32gcv-nofm.c | 4 +-
.../rvv/autovec/binop/vsub-rv32gcv-nofm.c | 4 +-
.../riscv/rvv/autovec/cmp/vcond-1.c | 48 ++++++++++++-
.../rvv/autovec/cond/cond_copysign-rv32gcv.c | 8 +--
.../riscv/rvv/autovec/cond/cond_fadd-1.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fadd-2.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fadd-3.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fadd-4.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fma_fnma-1.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fma_fnma-3.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fma_fnma-4.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fma_fnma-5.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fma_fnma-6.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmax-1.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmax-2.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmax-3.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmax-4.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmin-1.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmin-2.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmin-3.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmin-4.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fms_fnms-1.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fms_fnms-3.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fms_fnms-4.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fms_fnms-5.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fms_fnms-6.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmul-1.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmul-2.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmul-3.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmul-4.c | 4 +-
.../riscv/rvv/autovec/cond/cond_fmul-5.c | 4 +-
37 files changed, 162 insertions(+), 97 deletions(-)
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index d5793acc999..a7111172153 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -690,7 +690,7 @@ (define_expand "vec_cmp<mode><vm>"
[(set (match_operand:<VM> 0 "register_operand")
(match_operator:<VM> 1 "comparison_operator"
[(match_operand:V_VLSF 2 "register_operand")
- (match_operand:V_VLSF 3 "register_operand")]))]
+ (match_operand:V_VLSF 3 "nonmemory_operand")]))]
Note this may be too loose. Do we really want to allow any non-memory
operand or are you just trying to allow a few additional constants?
If the latter, then we should create a suitable predicate that allows a
register or just that set of constants rather than using nonmemory_operand.
Robin may have further comments.
jeff
