On Fri, May 10, 2024 at 3:18 PM Robin Dapp <rdapp....@gmail.com> wrote:
>
> Hi,
>
> this only forces the first comparison operator into a register if it is
> not already suitable.
>
> Bootstrap and regtest is running on x86 and aarch64, successful on p10.
> Regtested on riscv.
How does this make a difference in the end? I'd expect say forwprop to
fix things?
> gcc/ChangeLog:
>
> PR middle-end/113474
>
> * internal-fn.cc (expand_vec_cond_mask_optab_fn): Only force
> op1 to reg if necessary.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/autovec/pr113474.c: New test.
>
> Regards
> Robin
>
> ---
> gcc/internal-fn.cc | 3 ++-
> .../gcc.target/riscv/rvv/autovec/pr113474.c | 13 +++++++++++++
> 2 files changed, 15 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113474.c
>
> diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc
> index 2c764441cde..72cc6b7a1f7 100644
> --- a/gcc/internal-fn.cc
> +++ b/gcc/internal-fn.cc
> @@ -3164,7 +3164,8 @@ expand_vec_cond_mask_optab_fn (internal_fn, gcall
> *stmt, convert_optab optab)
> rtx_op2 = expand_normal (op2);
>
> mask = force_reg (mask_mode, mask);
> - rtx_op1 = force_reg (mode, rtx_op1);
> + if (!insn_operand_matches (icode, 1, rtx_op1))
> + rtx_op1 = force_reg (mode, rtx_op1);
>
> rtx target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);
> create_output_operand (&ops[0], target, mode);
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113474.c
> b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113474.c
> new file mode 100644
> index 00000000000..0364bf9f5e3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr113474.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile { target riscv_v } } */
> +/* { dg-additional-options "-std=c99" } */
> +
> +void
> +foo (int n, int **a)
> +{
> + int b;
> + for (b = 0; b < n; b++)
> + for (long e = 8; e > 0; e--)
> + a[b][e] = a[b][e] == 15;
> +}
> +
> +/* { dg-final { scan-assembler "vmerge.vim" } } */
> --
> 2.45.0
