From: Pan Li <pan2...@intel.com>
This patch would like to introduce one new gcc option for RVV. To
appoint the bits size of one RVV vector register. Valid arguments to
'-mrvv-vector-bits=' are:
* scalable
* zvl
The scalable will pick up the zvl*b in the march as the minimal vlen.
For example, the minimal vlen will be 512 when
march=rv64gcv_zvl512b and mrvv-vector-bits=scalable.
The zvl will pick up the zvl*b in the march as exactly vlen.
For example, the vlen will be 1024 exactly when
march=rv64gcv_zvl1024b and mrvv-vector-bits=zvl.
Given below sample:
void test_rvv_vector_bits ()
{
vint32m1_t x;
asm volatile ("def %0": "=vr"(x));
asm volatile (""::: "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
asm volatile ("use %0": : "vr"(x));
}
With -march=rv64gcv_zvl128b -mrvv-vector-bits=scalable we have (for min_vlen >=
128)
csrr t0,vlenb
sub sp,sp,t0
def v1
vs1r.v v1,0(sp)
vl1re32.v v1,0(sp)
use v1
csrr t0,vlenb
add sp,sp,t0
jr ra
With -march=rv64gcv_zvl128b -mrvv-vector-bits=zvl we have (for vlen = 128)
addi sp,sp,-16
def v1
vs1r.v v1,0(sp)
vl1re32.v v1,0(sp)
use v1
addi sp,sp,16
jr ra
The below test are passed for this patch.
* The riscv fully regression test.
gcc/ChangeLog:
* config/riscv/riscv-opts.h (enum rvv_vector_bits_enum): New enum for
different RVV vector bits.
* config/riscv/riscv.cc (riscv_convert_vector_bits): New func to
get the RVV vector bits, with given min_vlen.
(riscv_convert_vector_chunks): Combine the mrvv-vector-bits
option with min_vlen to RVV vector chunks.
(riscv_override_options_internal): Update comments and rename the
vector chunks.
* config/riscv/riscv.opt: Add option mrvv-vector-bits.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/rvv-vector-bits-1.c: New test.
* gcc.target/riscv/rvv/base/rvv-vector-bits-2.c: New test.
* gcc.target/riscv/rvv/base/rvv-vector-bits-3.c: New test.
* gcc.target/riscv/rvv/base/rvv-vector-bits-4.c: New test.
* gcc.target/riscv/rvv/base/rvv-vector-bits-5.c: New test.
* gcc.target/riscv/rvv/base/rvv-vector-bits-6.c: New test.
Signed-off-by: Pan Li <pan2...@intel.com>
---
gcc/config/riscv/riscv-opts.h | 8 +++++
gcc/config/riscv/riscv.cc | 35 +++++++++++++++----
gcc/config/riscv/riscv.opt | 14 ++++++++
.../riscv/rvv/base/rvv-vector-bits-1.c | 7 ++++
.../riscv/rvv/base/rvv-vector-bits-2.c | 7 ++++
.../riscv/rvv/base/rvv-vector-bits-3.c | 9 +++++
.../riscv/rvv/base/rvv-vector-bits-4.c | 9 +++++
.../riscv/rvv/base/rvv-vector-bits-5.c | 17 +++++++++
.../riscv/rvv/base/rvv-vector-bits-6.c | 17 +++++++++
9 files changed, 116 insertions(+), 7 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index 4edddbadc37..eefd2f9e01c 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -129,6 +129,14 @@ enum vsetvl_strategy_enum {
VSETVL_OPT_NO_FUSION,
};
+/* RVV vector bits for option -mrvv-vector-bits
+ zvl indicates take the bits of zvl*b provided by march as vector bits.
+ */
+enum rvv_vector_bits_enum {
+ RVV_VECTOR_BITS_SCALABLE,
+ RVV_VECTOR_BITS_ZVL,
+};
+
#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS &&
TARGET_64BIT))
/* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 5e984ee2a55..b6b133210ff 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8801,13 +8801,33 @@ riscv_init_machine_status (void)
return ggc_cleared_alloc<machine_function> ();
}
-/* Return the VLEN value associated with -march.
+static int
+riscv_convert_vector_bits (int min_vlen)
+{
+ int rvv_bits = 0;
+
+ switch (rvv_vector_bits)
+ {
+ case RVV_VECTOR_BITS_ZVL:
+ case RVV_VECTOR_BITS_SCALABLE:
+ rvv_bits = min_vlen;
+ break;
+ default:
+ gcc_unreachable ();
+ }
+
+ return rvv_bits;
+}
+
+/* Return the VLEN value associated with -march and -mwrvv-vector-bits.
TODO: So far we only support length-agnostic value. */
static poly_uint16
-riscv_convert_vector_bits (struct gcc_options *opts)
+riscv_convert_vector_chunks (struct gcc_options *opts)
{
int chunk_num;
int min_vlen = TARGET_MIN_VLEN_OPTS (opts);
+ int rvv_bits = riscv_convert_vector_bits (min_vlen);
+
if (min_vlen > 32)
{
/* When targetting minimum VLEN > 32, we should use 64-bit chunk size.
@@ -8826,7 +8846,7 @@ riscv_convert_vector_bits (struct gcc_options *opts)
- TARGET_MIN_VLEN = 2048bit: [256,256]
- TARGET_MIN_VLEN = 4096bit: [512,512]
FIXME: We currently DON'T support TARGET_MIN_VLEN > 4096bit. */
- chunk_num = min_vlen / 64;
+ chunk_num = rvv_bits / 64;
}
else
{
@@ -8847,8 +8867,9 @@ riscv_convert_vector_bits (struct gcc_options *opts)
compile-time constant if TARGET_VECTOR is disabled. */
if (TARGET_VECTOR_OPTS_P (opts))
{
- if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX)
- return (int) min_vlen / (riscv_bytes_per_vector_chunk * 8);
+ if (opts->x_riscv_autovec_preference == RVV_FIXED_VLMAX
+ || opts->x_rvv_vector_bits == RVV_VECTOR_BITS_ZVL)
+ return (int) rvv_bits / (riscv_bytes_per_vector_chunk * 8);
else
return poly_uint16 (chunk_num, chunk_num);
}
@@ -8920,8 +8941,8 @@ riscv_override_options_internal (struct gcc_options *opts)
if (TARGET_VECTOR && TARGET_BIG_ENDIAN)
sorry ("Current RISC-V GCC does not support RVV in big-endian mode");
- /* Convert -march to a chunks count. */
- riscv_vector_chunks = riscv_convert_vector_bits (opts);
+ /* Convert -march and -mrvv-vector-bits to a chunks count. */
+ riscv_vector_chunks = riscv_convert_vector_chunks (opts);
}
/* Implement TARGET_OPTION_OVERRIDE. */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 20685c42aed..bf60dcc8b53 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -607,3 +607,17 @@ Enum(stringop_strategy) String(vector)
Value(STRATEGY_VECTOR)
mstringop-strategy=
Target RejectNegative Joined Enum(stringop_strategy) Var(stringop_strategy)
Init(STRATEGY_AUTO)
Specify stringop expansion strategy.
+
+Enum
+Name(rvv_vector_bits) Type(enum rvv_vector_bits_enum)
+The possible RVV vector register lengths:
+
+EnumValue
+Enum(rvv_vector_bits) String(scalable) Value(RVV_VECTOR_BITS_SCALABLE)
+
+EnumValue
+Enum(rvv_vector_bits) String(zvl) Value(RVV_VECTOR_BITS_ZVL)
+
+mrvv-vector-bits=
+Target RejectNegative Joined Enum(rvv_vector_bits) Var(rvv_vector_bits)
Init(RVV_VECTOR_BITS_SCALABLE)
+-mrvv-vector-bits=zvl Set the number of bits in zvl for an RVV vector
register.
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
new file mode 100644
index 00000000000..20708460201
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-1.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64 -mrvv-vector-bits=128 -O3"
} */
+
+#include "riscv_vector.h"
+
+/* { dg-error "unrecognized argument in option '-mrvv-vector-bits=128'" "" {
target { "riscv*-*-*" } } 0 } */
+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable
zvl" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
new file mode 100644
index 00000000000..54c86ffcc56
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-2.c
@@ -0,0 +1,7 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64
-mrvv-vector-bits=invalid-bits -O3" } */
+
+#include "riscv_vector.h"
+
+/* { dg-error "unrecognized argument in option
'-mrvv-vector-bits=invalid-bits" "" { target { "riscv*-*-*" } } 0 } */
+/* { dg-message "note: valid arguments to '-mrvv-vector-bits=' are: scalable
zvl" "" { target { "riscv*-*-*" } } 0 } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
new file mode 100644
index 00000000000..9c9acebd5e3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-3.c
@@ -0,0 +1,9 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3"
} */
+
+void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
+{
+ for (int i = 0; i < 8; i++)
+ out[i] = a[i] + b[i];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
new file mode 100644
index 00000000000..9589bf81296
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-4.c
@@ -0,0 +1,9 @@
+/* Test that we do not have error when compile */
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable
-O3" } */
+
+void test_rvv_vector_bits_zvl (int *a, int *b, int *out)
+{
+ for (int i = 0; i < 8; i++)
+ out[i] = a[i] + b[i];
+}
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
new file mode 100644
index 00000000000..1f03bbce04f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-5.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=zvl -O3"
} */
+
+#include "riscv_vector.h"
+
+void test_rvv_vector_bits_zvl ()
+{
+ vint32m1_t x;
+ asm volatile ("def %0": "=vr"(x));
+ asm volatile (""::: "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
+ asm volatile ("use %0": : "vr"(x));
+}
+
+/* { dg-final { scan-assembler-not {csrr\s+[atx][0-9]+,\s*vlenb} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c
new file mode 100644
index 00000000000..ea762090457
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/rvv-vector-bits-6.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64 -mrvv-vector-bits=scalable
-O3" } */
+
+#include "riscv_vector.h"
+
+void test_rvv_vector_bits_scalable ()
+{
+ vint32m1_t x;
+ asm volatile ("def %0": "=vr"(x));
+ asm volatile (""::: "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
+ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
+ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
+ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31");
+ asm volatile ("use %0": : "vr"(x));
+}
+
+/* { dg-final { scan-assembler-times {csrr\s+[atx][0-9]+,\s*vlenb} 2 } } */
--
2.34.1
