> Yes. This is the last chance to walk around it here but we will end up with > more patterns. > since reduction dest operand always LMUL = 1 mode. > > So, when -march=rv64gcv, the dest mode should be V4SI, if > -march=rv64gcv_zvl256b, the dest mode should be V8SI. > ...etc. Different TARGET_MIN_VLEN, different M1 mode. It's going to be a big > change in RISC-V backend.
Hmm I haven't really thought this through yet (nor checked the spec in detail) but isn't the result always a 1-element thing? I.e. a V1SI regardless of the input vlen? That would also mean various changes of course. Regards Robin
