>> I'm not sure we'd want to model it as subreg here (endianness etc?).
>> Could we have a VLS-mode equivalent for the VLA mode that only holds
>> one element?
Yes. This is the last chance to walk around it here but we will end up with
more patterns.
since reduction dest operand always LMUL = 1 mode.
So, when -march=rv64gcv, the dest mode should be V4SI, if
-march=rv64gcv_zvl256b, the dest mode should be V8SI.
...etc. Different TARGET_MIN_VLEN, different M1 mode. It's going to be a big
change in RISC-V backend.
juzhe.zh...@rivai.ai
From: Robin Dapp
Date: 2023-12-11 17:01
To: Juzhe-Zhong; gcc-patches
CC: rdapp.gcc; richard.sandiford
Subject: Re: [PATCH] RTL-SSA: Fix ICE on record_use of RTL_SSA for RISC-V
VSETVL PASS
> In record_use:
>
> if (HARD_REGISTER_NUM_P (regno)
> && partial_subreg_p (use->mode (), mode))
>
> Assertion failed on partial_subreg_p which is:
>
> inline bool
> partial_subreg_p (machine_mode outermode, machine_mode innermode)
> {
> /* Modes involved in a subreg must be ordered. In particular, we must
> always know at compile time whether the subreg is paradoxical. */
> poly_int64 outer_prec = GET_MODE_PRECISION (outermode);
> poly_int64 inner_prec = GET_MODE_PRECISION (innermode);
> gcc_checking_assert (ordered_p (outer_prec, inner_prec));
> -----> cause ICE.
> return maybe_lt (outer_prec, inner_prec);
> }
>
> RISC-V VSETVL PASS is an advanced lazy vsetvl insertion PASS after RA
> (register allocation).
>
> The rootcause is that we have a pattern (reduction instruction) that includes
> both VLA (length-agnostic) and VLS (fixed-length) modes.
Maybe as additional context: The second input (which has a VLA mode here)
is not used entirely but just its first element. This serves as initial
value for the reduction.
I'm not sure we'd want to model it as subreg here (endianness etc?).
Could we have a VLS-mode equivalent for the VLA mode that only holds
one element?
Regards
Robin
