The 11/29/2023 15:15, Richard Earnshaw wrote:
> On 13/11/2023 11:37, Victor Do Nascimento wrote:
> > +/* LSE128 atomic support encoded in ID_AA64ISAR0_EL1.Atomic,
> > + bits[23:20]. The expected value is 0b0011. Check that. */
> > +#define HAS_LSE128() ({ \
> > + unsigned long val; \
> > + asm volatile ("mrs %0, ID_AA64ISAR0_EL1" : "=r" (val)); \
> > + (val & 0xf00000) >= 0x300000; \
> > + })
> > +
>
> The pseudo-code for this register reads:
>
> if PSTATE.EL == EL0 then
> if IsFeatureImplemented(FEAT_IDST) then
> if EL2Enabled() && HCR_EL2.TGE == '1' then
> AArch64.SystemAccessTrap(EL2, 0x18);
> else
> AArch64.SystemAccessTrap(EL1, 0x18);
> else
> UNDEFINED;
> ...
>
> So this instruction may result in SIGILL if run on cores without FEAT_IDST.
> SystemAccessTrap just punts the problem up to the kernel or hypervisor as
> well.
yes, HWCAP_CPUID has to be checked to see if
linux traps and emulates the mrs for userspace.
> I think we need a hwcap bit to work this out, which is the preferred way on
yes, use hwcap instead of id reg (hwcap2 is
passed to aarch64 ifuncs or __getauxval works)
> Linux anyway. Something like this? :)
> https://lore.kernel.org/linux-arm-kernel/20231003124544.858804-2-joey.go...@arm.com/T/
note that there was no linux release since this
got added.
we can add the hwcap values tentatively, but
there is a risk of revert on the kernel side
(which means libatomic vs linux abi break) so
i would only commit the patch into gcc after
a linux release is tagged.
