Jakub Jelinek <ja...@redhat.com> writes:
> Hi!
>
> The aarch64_simd_stp<mode> pattern uses w constraint in one alternative and
> r in another, but for the latter incorrectly uses <vw> iterator in %<vw>1
> which
> expands to %d1 for V2DF and %s1 for V2SF and V4SF (this one not relevant to
> the pattern) and %w1 for others, so it ICEs if the alternative is selected
> during final. Compared to this, <vwcore> macro has the same values for all
> modes but uses w for V2DF and V2SF.
>
> Bootstrapped/regtested on aarch64-linux, ok for trunk?
>
> 2023-11-24 Andrew Pinski <pins...@gmail.com>
> Jakub Jelinek <ja...@redhat.com>
>
> PR target/109977
> * config/aarch64/aarch64-simd.md (aarch64_simd_stp<mode>): Use <vwcore>
> rather than %<vw> for alternative with r constraint on input operand.
>
> * gcc.dg/pr109977.c: New test.
OK, thanks.
Richard
> --- gcc/config/aarch64/aarch64-simd.md.jj 2023-11-22 22:55:20.577075762
> +0100
> +++ gcc/config/aarch64/aarch64-simd.md 2023-11-24 12:51:22.855215700
> +0100
> @@ -269,7 +269,7 @@ (define_insn "aarch64_simd_stp<mode>"
> "TARGET_SIMD"
> {@ [ cons: =0 , 1 ; attrs: type ]
> [ Umn , w ; neon_stp ] stp\t%<Vetype>1, %<Vetype>1,
> %y0
> - [ Umn , r ; store_<ldpstp_vel_sz> ] stp\t%<vw>1, %<vw>1, %y0
> + [ Umn , r ; store_<ldpstp_vel_sz> ] stp\t%<vwcore>1, %<vwcore>1,
> %y0
> }
> )
>
> --- gcc/testsuite/gcc.dg/pr109977.c.jj 2023-11-24 12:51:04.551473591
> +0100
> +++ gcc/testsuite/gcc.dg/pr109977.c 2023-11-24 12:50:44.158760916 +0100
> @@ -0,0 +1,16 @@
> +/* PR target/109977 */
> +/* { dg-do compile } */
> +/* { dg-options "-Og" } */
> +
> +typedef double __attribute__((__vector_size__ (8))) V;
> +typedef double __attribute__((__vector_size__ (16))) W;
> +V v;
> +int i;
> +extern void bar (void *);
> +
> +void
> +foo (void)
> +{
> + W w = __builtin_shufflevector (v, (W) { }, 0, 0);
> + bar (&w);
> +}
>
> Jakub
