PR target/112561
gcc/ChangeLog:
* config/riscv/riscv-v.cc (expand_tuple_move): Fix bug.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr112561.c: New test.
---
gcc/config/riscv/riscv-v.cc | 4 ++++
.../gcc.target/riscv/rvv/autovec/pr112561.c | 16 ++++++++++++++++
2 files changed, 20 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 6a2009ffb05..f769c1474e0 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -2148,6 +2148,10 @@ expand_tuple_move (rtx *ops)
offset = ops[2];
}
+ /* Non-fractional LMUL has whole register moves that don't require a
+ vsetvl for VLMAX. */
+ if (fractional_p)
+ emit_vlmax_vsetvl (subpart_mode, ops[4]);
if (MEM_P (ops[1]))
{
/* Load operations. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
new file mode 100644
index 00000000000..25e61fa12c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-options "-O3 -ftree-vectorize
--param=riscv-autovec-preference=fixed-vlmax -mcmodel=medlow" } */
+
+int printf(char *, ...);
+int a, b, c, e;
+short d[7][7] = {};
+int main() {
+ short f;
+ c = 0;
+ for (; c <= 6; c++) {
+ e |= d[c][c] & 1;
+ b &= f & 3;
+ }
+ printf("%d\n", a);
+ return 0;
+}
--
2.36.3
