> diff --git a/gcc/config/riscv/riscv_th_vector.h
> b/gcc/config/riscv/riscv_th_vector.h
> new file mode 100644
> index 00000000000..194652032bc
> --- /dev/null
> +++ b/gcc/config/riscv/riscv_th_vector.h
...
> +/* NOTE: This implementation of riscv_vector.h is intentionally short. It
> does
> + not define the RVV types and intrinsic functions directly in C and C++
> + code, but instead uses the following pragma to tell GCC to insert the
> + necessary type and function definitions itself. The net effect is the
> + same, and the file is a complete implementation of riscv_vector.h. */
> +#pragma riscv intrinsic "vector"
Plz use #pragma riscv intrinsic "thead_vector"
> @@ -1135,7 +1135,7 @@ (define_expand "@mov<V_FRACT:mode><P:mode>_lra"
> [(set (match_operand:V_FRACT 0 "reg_or_mem_operand")
> (match_operand:V_FRACT 1 "reg_or_mem_operand"))
> (clobber (match_scratch:P 2))])]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
It's an accident, right?
> {})
>
> (define_expand "@mov<VB:mode><P:mode>_lra"
> @@ -1143,14 +1143,14 @@ (define_expand "@mov<VB:mode><P:mode>_lra"
> [(set (match_operand:VB 0 "reg_or_mem_operand")
> (match_operand:VB 1 "reg_or_mem_operand"))
> (clobber (match_scratch:P 2))])]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Ditto.
> {})
>
> (define_insn_and_split "*mov<V_FRACT:mode><P:mode>_lra"
> [(set (match_operand:V_FRACT 0 "reg_or_mem_operand" "=vr, m,vr")
> (match_operand:V_FRACT 1 "reg_or_mem_operand" " m,vr,vr"))
> (clobber (match_scratch:P 2 "=&r,&r,X"))]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Ditto.
> "#"
> "&& reload_completed"
> [(const_int 0)]
> @@ -1172,7 +1172,7 @@ (define_insn_and_split "*mov<VB:mode><P:mode>_lra"
> [(set (match_operand:VB 0 "reg_or_mem_operand" "=vr, m,vr")
> (match_operand:VB 1 "reg_or_mem_operand" " m,vr,vr"))
> (clobber (match_scratch:P 2 "=&r,&r,X"))]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Ditto.
> "#"
> "&& reload_completed"
> [(const_int 0)]
> @@ -1286,14 +1286,14 @@ (define_expand "@mov<VLS_AVL_REG:mode><P:mode>_lra"
> [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand")
> (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand"))
> (clobber (match_scratch:P 2))])]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)"
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)"
Ditto.
> {})
>
> (define_insn_and_split "*mov<VLS_AVL_REG:mode><P:mode>_lra"
> [(set (match_operand:VLS_AVL_REG 0 "reg_or_mem_operand" "=vr, m,vr")
> (match_operand:VLS_AVL_REG 1 "reg_or_mem_operand" " m,vr,vr"))
> (clobber (match_scratch:P 2 "=&r,&r,X"))]
> - "TARGET_VECTOR && (lra_in_progress || reload_completed)
> + "TARGET_VECTOR && (lra_in_progress || reload_completed)
Ditto.
> && (register_operand (operands[0], <VLS_AVL_REG:MODE>mode)
> || register_operand (operands[1], <VLS_AVL_REG:MODE>mode))"
> "#"
> @@ -1359,7 +1359,7 @@ (define_expand "movmisalign<mode>"
> (define_expand "movmisalign<mode>"
> [(set (match_operand:V 0 "nonimmediate_operand")
> (match_operand:V 1 "general_operand"))]
> - "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
> + "TARGET_VECTOR && TARGET_VECTOR_MISALIGN_SUPPORTED"
Ditto.
> {
> emit_move_insn (operands[0], operands[1]);
> DONE;
> @@ -1396,7 +1396,7 @@ (define_insn_and_split "*vec_duplicate<mode>"
> [(set (match_operand:V_VLS 0 "register_operand")
> (vec_duplicate:V_VLS
> (match_operand:<VEL> 1 "direct_broadcast_operand")))]
> - "TARGET_VECTOR && can_create_pseudo_p ()"
> + "TARGET_VECTOR && can_create_pseudo_p ()"
Ditto.
> "#"
> "&& 1"
> [(const_int 0)]
