On Sat, Nov 18, 2023 at 12:27 PM Jun Sha (Joshua)
<cooper.jos...@linux.alibaba.com> wrote:
>
> This patch is to introduce basic XTheadVector support
> (march string parsing and a test for __riscv_xtheadvector)
> according to https://github.com/T-head-Semi/thead-extension-spec/
>
> Contributors:
> Jun Sha (Joshua) <cooper.jos...@linux.alibaba.com>
> Jin Ma <ji...@linux.alibaba.com>
> Christoph Müllner <christoph.muell...@vrull.eu>
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc
> (riscv_subset_list::parse): : Add new vendor extension.
> * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins):
> Add test marco.
> * config/riscv/riscv.opt: Add new mask.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/predef-__riscv_th_v_intrinsic.c: New test.
> * gcc.target/riscv/rvv/xtheadvector.c: New test.
> ---
> gcc/common/config/riscv/riscv-common.cc | 10 ++++++++++
> gcc/config/riscv/riscv-c.cc | 4 ++++
> gcc/config/riscv/riscv.opt | 2 ++
> .../riscv/predef-__riscv_th_v_intrinsic.c | 11 +++++++++++
> gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c | 13 +++++++++++++
> 5 files changed, 40 insertions(+)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/predef-__riscv_th_v_intrinsic.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc
> b/gcc/common/config/riscv/riscv-common.cc
> index 526dbb7603b..914924171fd 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -75,6 +75,8 @@ static const riscv_implied_info_t riscv_implied_info[] =
>
> {"v", "zvl128b"},
> {"v", "zve64d"},
> + {"xtheadvector", "zvl128b"},
> + {"xtheadvector", "zve64d"},
^^^ don't imply zve64d, it will mix V 1.0 together, I know why you
want to do that, so I have given some suggestions below.
>
> {"zve32f", "f"},
> {"zve64f", "f"},
> @@ -325,6 +327,7 @@ static const struct riscv_ext_version
> riscv_ext_version_table[] =
> {"xtheadmemidx", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xtheadmempair", ISA_SPEC_CLASS_NONE, 1, 0},
> {"xtheadsync", ISA_SPEC_CLASS_NONE, 1, 0},
> + {"xtheadvector", ISA_SPEC_CLASS_NONE, 1, 0},
>
> {"xventanacondops", ISA_SPEC_CLASS_NONE, 1, 0},
>
> @@ -1495,6 +1498,10 @@ riscv_subset_list::parse (const char *arch, location_t
> loc)
> error_at (loc, "%<-march=%s%>: z*inx conflicts with floating-point "
> "extensions", arch);
>
> + if (subset_list->lookup ("v") && subset_list->lookup ("xtheadvector"))
> + error_at (loc, "%<-march=%s%>: xtheadvector conflicts with vector "
> + "extensions", arch);
> +
> /* 'H' hypervisor extension requires base ISA with 32 registers. */
> if (subset_list->lookup ("e") && subset_list->lookup ("h"))
> error_at (loc, "%<-march=%s%>: h extension requires i extension", arch);
> @@ -1680,6 +1687,9 @@ static const riscv_ext_flag_table_t
> riscv_ext_flag_table[] =
> {"xtheadmemidx", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMIDX},
> {"xtheadmempair", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADMEMPAIR},
> {"xtheadsync", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADSYNC},
> + {"xtheadvector", &gcc_options::x_riscv_xthead_subext, MASK_XTHEADVECTOR},
> + {"xtheadvector", &gcc_options::x_target_flags, MASK_FULL_V},
> + {"xtheadvector", &gcc_options::x_target_flags, MASK_VECTOR},
Add following two line then you don't need zve64d
{"xtheadvector", &gcc_options::x_riscv_vector_elen_flags, MASK_VECTOR_ELEN_64},
{"xtheadvector", &gcc_options::x_riscv_vector_elen_flags,
MASK_VECTOR_ELEN_FP_64},
>
> {"xventanacondops", &gcc_options::x_riscv_xventana_subext,
> MASK_XVENTANACONDOPS},
>
