I can understand why remove mem to mem pattern, but why the normal mov
pattern for VLS_AVL_IMM need to change too?
On Wed, Sep 27, 2023 at 10:39 AM juzhe.zh...@rivai.ai
<juzhe.zh...@rivai.ai> wrote:
>
> >> Why add `can_create_pseudo_p ()` here? this will split after reload,
> >> but we forbid that pattern between reload and split2?
>
> I have no ideal. Some fortran tests just need recognization of mem-to-mem
> pattern before RA.
> I don't know the reason.
>
> ________________________________
> juzhe.zh...@rivai.ai
>
>
> From: Kito Cheng
> Date: 2023-09-27 17:33
> To: Juzhe-Zhong
> CC: gcc-patches; kito.cheng; jeffreyalaw; rdapp.gcc
> Subject: Re: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566]
> > (define_insn_and_split "*mov<mode>"
> > [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr")
> > (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))]
> > "TARGET_VECTOR
> > - && (register_operand (operands[0], <MODE>mode)
> > + && (can_create_pseudo_p ()
>
> Why add `can_create_pseudo_p ()` here? this will split after reload,
> but we forbid that pattern between reload and split2?
>
> > + || register_operand (operands[0], <MODE>mode)
> > || register_operand (operands[1], <MODE>mode))"
> > "@
> > #
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> > index aedf98819bb..24bb7240db8 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c
> > @@ -4,54 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** lbu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sb\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (int8_t *in, int8_t *out)
> > -{
> > - v1qi v = *(v1qi*)in;
> > - *(v1qi*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (int8_t *in, int8_t *out)
> > -{
> > - v2qi v = *(v2qi*)in;
> > - *(v2qi*)out = v;
> > -}
> > -
> > -/*
> > -** mov2:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov2 (int8_t *in, int8_t *out)
> > -{
> > - v4qi v = *(v4qi*)in;
> > - *(v4qi*)out = v;
> > -}
> > -
> > -/*
> > -** mov3:
> > -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov3 (int8_t *in, int8_t *out)
> > -{
> > - v8qi v = *(v8qi*)in;
> > - *(v8qi*)out = v;
> > -}
> > -
> > /*
> > ** mov4:
> > ** vsetivli\s+zero,\s*16,\s*e8,\s*mf8,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> > index 5e9615412b7..cae96b3be3f 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c
> > @@ -4,18 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (double *in, double *out)
> > -{
> > - v1df v = *(v1df*)in;
> > - *(v1df*)out = v;
> > -}
> > -
> > /*
> > ** mov1:
> > ** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
> > deleted file mode 100644
> > index 10ae1972db7..00000000000
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c
> > +++ /dev/null
> > @@ -1,19 +0,0 @@
> > -/* { dg-do compile } */
> > -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3
> > -fno-schedule-insns -fno-schedule-insns2" } */
> > -/* { dg-final { check-function-bodies "**" "" } } */
> > -
> > -#include "def.h"
> > -
> > -/*
> > -** mov:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov (int8_t *in, int8_t *out)
> > -{
> > - v8qi v = *(v8qi*)in;
> > - *(v8qi*)out = v;
> > -}
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> > index f2880ae5e77..86ce22896c5 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c
> > @@ -4,42 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (int16_t *in, int16_t *out)
> > -{
> > - v1hi v = *(v1hi*)in;
> > - *(v1hi*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (int16_t *in, int16_t *out)
> > -{
> > - v2hi v = *(v2hi*)in;
> > - *(v2hi*)out = v;
> > -}
> > -
> > -/*
> > -** mov2:
> > -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov2 (int16_t *in, int16_t *out)
> > -{
> > - v4hi v = *(v4hi*)in;
> > - *(v4hi*)out = v;
> > -}
> > -
> > /*
> > ** mov3:
> > ** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
> > deleted file mode 100644
> > index f81f1697d65..00000000000
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c
> > +++ /dev/null
> > @@ -1,19 +0,0 @@
> > -/* { dg-do compile } */
> > -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3
> > -fno-schedule-insns -fno-schedule-insns2" } */
> > -/* { dg-final { check-function-bodies "**" "" } } */
> > -
> > -#include "def.h"
> > -
> > -/*
> > -** mov:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov (int16_t *in, int16_t *out)
> > -{
> > - v4hi v = *(v4hi*)in;
> > - *(v4hi*)out = v;
> > -}
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> > index c30ed8f76f5..04475207966 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c
> > @@ -4,30 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (int32_t *in, int32_t *out)
> > -{
> > - v1si v = *(v1si*)in;
> > - *(v1si*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (int32_t *in, int32_t *out)
> > -{
> > - v2si v = *(v2si*)in;
> > - *(v2si*)out = v;
> > -}
> > -
> > /*
> > ** mov2:
> > ** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
> > deleted file mode 100644
> > index d6dbff1caa9..00000000000
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c
> > +++ /dev/null
> > @@ -1,19 +0,0 @@
> > -/* { dg-do compile } */
> > -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3
> > -fno-schedule-insns -fno-schedule-insns2" } */
> > -/* { dg-final { check-function-bodies "**" "" } } */
> > -
> > -#include "def.h"
> > -
> > -/*
> > -** mov:
> > -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov (int32_t *in, int32_t *out)
> > -{
> > - v2si v = *(v2si*)in;
> > - *(v2si*)out = v;
> > -}
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> > index 46509e367c3..d0674a47a14 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c
> > @@ -4,18 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (int64_t *in, int64_t *out)
> > -{
> > - v1di v = *(v1di*)in;
> > - *(v1di*)out = v;
> > -}
> > -
> > /*
> > ** mov1:
> > ** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> > index 1cba7ddad94..b905c74d43b 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c
> > @@ -4,42 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** flh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsh\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (_Float16 *in, _Float16 *out)
> > -{
> > - v1hf v = *(v1hf*)in;
> > - *(v1hf*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (_Float16 *in, _Float16 *out)
> > -{
> > - v2hf v = *(v2hf*)in;
> > - *(v2hf*)out = v;
> > -}
> > -
> > -/*
> > -** mov2:
> > -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov2 (_Float16 *in, _Float16 *out)
> > -{
> > - v4hf v = *(v4hf*)in;
> > - *(v4hf*)out = v;
> > -}
> > -
> > /*
> > ** mov3:
> > ** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> > b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> > index 0773f6a70f3..5f9bc052e97 100644
> > --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c
> > @@ -4,30 +4,6 @@
> >
> > #include "def.h"
> >
> > -/*
> > -** mov0:
> > -** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov0 (float *in, float *out)
> > -{
> > - v1sf v = *(v1sf*)in;
> > - *(v1sf*)out = v;
> > -}
> > -
> > -/*
> > -** mov1:
> > -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\)
> > -** ret
> > -*/
> > -void mov1 (float *in, float *out)
> > -{
> > - v2sf v = *(v2sf*)in;
> > - *(v2sf*)out = v;
> > -}
> > -
> > /*
> > ** mov2:
> > ** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au]
> > diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
> > b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
> > new file mode 100644
> > index 00000000000..2e30dc9bfaa
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90
> > @@ -0,0 +1,31 @@
> > +! { dg-do compile }
> > +! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast
> > -fallow-argument-mismatch -fmax-stack-var-size=65536 -S -std=legacy -w" }
> > +
> > +module a
> > + integer,parameter :: SHR_KIND_R8 = selected_real_kind(12)
> > +end module a
> > +module b
> > + use a, c => shr_kind_r8
> > +contains
> > + subroutine d(cg , km, i1, i2)
> > + real (c) ch(i2,km)
> > + real (c) cg(4,i1:i2,km)
> > + real dc(i2,km)
> > + real(c) ci(i2,km)
> > + real(c) cj(i2,km)
> > + do k=2,ck
> > + do i=i1,0
> > + cl = ci(i,k) *ci(i,1) / cj(i,k)+ch(i,1)
> > + cm = cg(1,i,k) - min(e,cg(1,i,co))
> > + dc(i,k) = sign(cm, cl)
> > + enddo
> > + enddo
> > + if ( cq == 0 ) then
> > + do i=i1,i2
> > + if( cr <= cs ) then
> > + cg= sign( min(ct, cg), cg)
> > + endif
> > + enddo
> > + endif
> > + end subroutine d
> > +end module b
> > --
> > 2.36.3
> >
>
