Currently, autovec_length_operand predicate incorrect configuration is
discovered in PR110989 since this following situation:
vect__6.24_107 = .MASK_LEN_LOAD (vectp.22_105, 32B, mask__49.21_99,
POLY_INT_CST [2, 2], 0); ---> dummy length = VF.
The current autovec length operand failed to recognize the VF dummy length.
-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast
-fno-schedule-insns -fno-schedule-insns2:
Before this patch:
srli a4,s0,2
addi a4,a4,-3
srli s0,s0,3
vsetvli a5,zero,e64,m1,ta,ma
vid.v v1
vmul.vx v1,v1,a4
addi a4,s0,-2
vadd.vx v1,v1,a4
addi a4,s0,-1
vslide1up.vx v2,v1,a4
vmv.v.x v1,a4
vand.vv v1,v2,v1
vl1re64.v v3,0(t2)
vrgather.vv v2,v3,v1
vmv.v.i v1,0
vmfeq.vv v0,v2,v1
vsetvli zero,s0,e32,mf2,ta,ma ---> s0 = POLY (2,2)
vle32.v v3,0(t3),v0.t
vsetvli a5,zero,e64,m1,ta,ma
vmfne.vv v0,v2,v1
vsetvli zero,zero,e32,mf2,ta,ma
vfwcvt.f.x.v v1,v3
vsetvli zero,zero,e64,m1,ta,ma
vmerge.vvm v1,v1,v2,v0
vslidedown.vx v1,v1,a4
vfmv.f.s fa5,v1
j .L6
After this patch:
srli a4,s0,2
addi a4,a4,-3
srli s0,s0,3
vsetvli a5,zero,e64,m1,ta,ma
vid.v v1
vmul.vx v1,v1,a4
addi a4,s0,-2
vadd.vx v1,v1,a4
addi s0,s0,-1
vslide1up.vx v2,v1,s0
vmv.v.x v1,s0
vand.vv v1,v2,v1
vl1re64.v v3,0(t2)
vrgather.vv v2,v3,v1
vmv.v.i v1,0
vmfeq.vv v0,v2,v1
vle32.v v3,0(t3),v0.t
vmfne.vv v0,v2,v1
vsetvli zero,zero,e32,mf2,ta,ma
vfwcvt.f.x.v v1,v3
vsetvli zero,zero,e64,m1,ta,ma
vmerge.vvm v1,v1,v2,v0
vslidedown.vx v1,v1,s0
vfmv.f.s fa5,v1
j .L6
2 vsetvli insns are reduced.
gcc/ChangeLog:
* config/riscv/predicates.md: Fix predicate.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr110989.c: Add vsetvli assembly check.
---
gcc/config/riscv/predicates.md | 5 +----
gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c | 7 ++++++-
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md
index 9db28c2def7..b6ebdcf55de 100644
--- a/gcc/config/riscv/predicates.md
+++ b/gcc/config/riscv/predicates.md
@@ -282,10 +282,7 @@
(define_special_predicate "autovec_length_operand"
(ior (match_operand 0 "pmode_register_operand")
- (ior (match_operand 0 "const_csr_operand")
- (match_test "rtx_equal_p (op, gen_int_mode
- (GET_MODE_NUNITS (GET_MODE (op)),
- Pmode))"))))
+ (match_code "const_int,const_poly_int")))
(define_predicate "reg_or_mem_operand"
(ior (match_operand 0 "register_operand")
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c
index cf3b247e604..6e163a55c56 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr110989.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gcv -mabi=lp64d
--param=riscv-autovec-preference=scalable -Ofast" } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d
--param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns
-fno-schedule-insns2" } */
int a, b, c;
double *d;
@@ -9,3 +9,8 @@ void e() {
f = *d ?: *(&a + c);
b = f;
}
+
+/* { dg-final { scan-assembler-times {vsetvli} 3 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*zero,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 } } */
--
2.36.1
