Factorize
vhaddq_n, vhsubq_n, vqaddq_n, vqdmulhq_n, vqrdmulhq_n, vqsubq_n
so that they use the same pattern.
2022-09-08 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MVE_INT_SU_N_BINARY): New.
(mve_insn): Add vhaddq, vhsubq, vqaddq, vqdmulhq, vqrdmulhq,
vqsubq.
(supf): Add VQDMULHQ_N_S, VQRDMULHQ_N_S.
* config/arm/mve.md (mve_vhaddq_n_<supf><mode>)
(mve_vhsubq_n_<supf><mode>, mve_vqaddq_n_<supf><mode>)
(mve_vqdmulhq_n_s<mode>, mve_vqrdmulhq_n_s<mode>)
(mve_vqsubq_n_<supf><mode>): Merge into ...
(@mve_<mve_insn>q_n_<supf><mode>): ... this.
---
gcc/config/arm/iterators.md | 17 ++++++++
gcc/config/arm/mve.md | 86 ++++---------------------------------
2 files changed, 25 insertions(+), 78 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 18d70350bbe..6dbc40f842c 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -390,6 +390,15 @@ (define_int_iterator MVE_INT_N_BINARY [
VSUBQ_N_S VSUBQ_N_U
])
+(define_int_iterator MVE_INT_SU_N_BINARY [
+ VHADDQ_N_S VHADDQ_N_U
+ VHSUBQ_N_S VHSUBQ_N_U
+ VQADDQ_N_S VQADDQ_N_U
+ VQDMULHQ_N_S
+ VQRDMULHQ_N_S
+ VQSUBQ_N_S VQSUBQ_N_U
+ ])
+
(define_int_iterator MVE_INT_N_BINARY_LOGIC [
VBICQ_N_S VBICQ_N_U
VORRQ_N_S VORRQ_N_U
@@ -442,7 +451,9 @@ (define_int_attr mve_insn [
(VCREATEQ_S "vcreate") (VCREATEQ_U "vcreate") (VCREATEQ_F
"vcreate")
(VEORQ_M_S "veor") (VEORQ_M_U "veor") (VEORQ_M_F "veor")
(VHADDQ_M_S "vhadd") (VHADDQ_M_U "vhadd")
+ (VHADDQ_N_S "vhadd") (VHADDQ_N_U "vhadd")
(VHSUBQ_M_S "vhsub") (VHSUBQ_M_U "vhsub")
+ (VHSUBQ_N_S "vhsub") (VHSUBQ_N_U "vhsub")
(VMAXQ_M_S "vmax") (VMAXQ_M_U "vmax")
(VMINQ_M_S "vmin") (VMINQ_M_U "vmin")
(VMULHQ_M_S "vmulh") (VMULHQ_M_U "vmulh")
@@ -453,19 +464,23 @@ (define_int_attr mve_insn [
(VORRQ_M_S "vorr") (VORRQ_M_U "vorr") (VORRQ_M_F "vorr")
(VORRQ_N_S "vorr") (VORRQ_N_U "vorr")
(VQADDQ_M_S "vqadd") (VQADDQ_M_U "vqadd")
+ (VQADDQ_N_S "vqadd") (VQADDQ_N_U "vqadd")
(VQDMLADHQ_M_S "vqdmladh")
(VQDMLADHXQ_M_S "vqdmladhx")
(VQDMLSDHQ_M_S "vqdmlsdh")
(VQDMLSDHXQ_M_S "vqdmlsdhx")
(VQDMULHQ_M_S "vqdmulh")
+ (VQDMULHQ_N_S "vqdmulh")
(VQRDMLADHQ_M_S "vqrdmladh")
(VQRDMLADHXQ_M_S "vqrdmladhx")
(VQRDMLSDHQ_M_S "vqrdmlsdh")
(VQRDMLSDHXQ_M_S "vqrdmlsdhx")
(VQRDMULHQ_M_S "vqrdmulh")
+ (VQRDMULHQ_N_S "vqrdmulh")
(VQRSHLQ_M_S "vqrshl") (VQRSHLQ_M_U "vqrshl")
(VQSHLQ_M_S "vqshl") (VQSHLQ_M_U "vqshl")
(VQSUBQ_M_S "vqsub") (VQSUBQ_M_U "vqsub")
+ (VQSUBQ_N_S "vqsub") (VQSUBQ_N_U "vqsub")
(VRHADDQ_M_S "vrhadd") (VRHADDQ_M_U "vrhadd")
(VRMULHQ_M_S "vrmulh") (VRMULHQ_M_U "vrmulh")
(VRSHLQ_M_S "vrshl") (VRSHLQ_M_U "vrshl")
@@ -1619,6 +1634,8 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U
"u") (VREV16Q_S "s")
(VQRDMLSDHQ_M_S "s")
(VQRDMLSDHXQ_M_S "s")
(VQRDMULHQ_M_S "s")
+ (VQDMULHQ_N_S "s")
+ (VQRDMULHQ_N_S "s")
])
;; Both kinds of return insn.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 21c54197db5..3377e03ee06 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -1015,16 +1015,21 @@ (define_expand "mve_veorq_s<mode>"
;;
;; [vhaddq_n_u, vhaddq_n_s])
+;; [vhsubq_n_u, vhsubq_n_s])
+;; [vqaddq_n_s, vqaddq_n_u])
+;; [vqdmulhq_n_s])
+;; [vqrdmulhq_n_s])
+;; [vqsubq_n_s, vqsubq_n_u])
;;
-(define_insn "mve_vhaddq_n_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_n_<supf><mode>"
[
(set (match_operand:MVE_2 0 "s_register_operand" "=w")
(unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:<V_elem> 2 "s_register_operand" "r")]
- VHADDQ_N))
+ MVE_INT_SU_N_BINARY))
]
"TARGET_HAVE_MVE"
- "vhadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
+ "<mve_insn>.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
[(set_attr "type" "mve_move")
])
@@ -1073,21 +1078,6 @@ (define_insn "mve_vhcaddq_rot90_s<mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vhsubq_n_u, vhsubq_n_s])
-;;
-(define_insn "mve_vhsubq_n_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VHSUBQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vhsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vhsubq_s, vhsubq_u])
;;
@@ -1415,21 +1405,6 @@ (define_expand "mve_vorrq_u<mode>"
"TARGET_HAVE_MVE"
)
-;;
-;; [vqaddq_n_s, vqaddq_n_u])
-;;
-(define_insn "mve_vqaddq_n_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VQADDQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vqadd.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vqaddq_u, vqaddq_s])
;;
@@ -1445,21 +1420,6 @@ (define_insn "mve_vqaddq_<supf><mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vqdmulhq_n_s])
-;;
-(define_insn "mve_vqdmulhq_n_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VQDMULHQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vqdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vqdmulhq_s])
;;
@@ -1475,21 +1435,6 @@ (define_insn "mve_vqdmulhq_s<mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vqrdmulhq_n_s])
-;;
-(define_insn "mve_vqrdmulhq_n_s<mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VQRDMULHQ_N_S))
- ]
- "TARGET_HAVE_MVE"
- "vqrdmulh.s%#<V_sz_elem>\t%q0, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vqrdmulhq_s])
;;
@@ -1595,21 +1540,6 @@ (define_insn "mve_vqshluq_n_s<mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vqsubq_n_s, vqsubq_n_u])
-;;
-(define_insn "mve_vqsubq_n_<supf><mode>"
- [
- (set (match_operand:MVE_2 0 "s_register_operand" "=w")
- (unspec:MVE_2 [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:<V_elem> 2 "s_register_operand" "r")]
- VQSUBQ_N))
- ]
- "TARGET_HAVE_MVE"
- "vqsub.<supf>%#<V_sz_elem>\t%q0, %q1, %2"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vqsubq_u, vqsubq_s])
;;
--
2.34.1
