[PATCH] aarch64: Reimplement vshrn_high_n* intrinsics using builtins

[Kyrylo Tkachov via Gcc-patches]

Hi all,

This patch reimplements the vshrn_high_n* intrinsics that generate the SHRN2 
instruction.
It is a vec_concat of the narrowing shift with the bottom part of the 
destination register,
so we need a little-endian and a big-endian version and an expander to pick 
between them.

Bootstrapped and tested on aarch64-none-linux-gnu and aarch64_be-none-elf.
Pushing to trunk.
Thanks,
Kyrill

gcc/ChangeLog:

        * config/aarch64/aarch64-simd-builtins.def (shrn2): Define builtin.
        * config/aarch64/aarch64-simd.md (aarch64_shrn2<mode>_insn_le): Define.
        (aarch64_shrn2<mode>_insn_be): Likewise.
        (aarch64_shrn2<mode>): Likewise.
        * config/aarch64/arm_neon.h (vshrn_high_n_s16): Reimlplement using
        builtins.
        (vshrn_high_n_s32): Likewise.
        (vshrn_high_n_s64): Likewise.
        (vshrn_high_n_u16): Likewise.
        (vshrn_high_n_u32): Likewise.
        (vshrn_high_n_u64): Likewise.

vshrn-hi.patch
Description: vshrn-hi.patch