Joel Hutton <joel.hut...@arm.com> writes:
> Tests are still running, but I believe I've addressed the comment.
>
>> There are ways in which we could reduce the amount of cut-&-paste here,
>> but I guess everything is a trade-off between clarity and compactness.
>> One extreme is to write them all out explicitly, another extreme would
>> be to have one define_expand and various iterators and attributes.
>>
>> I think the vec_widen_<su>mult_*_<mode> patterns strike a good balance:
>> the use ANY_EXTEND to hide the sign difference while still having
>> separate hi and lo patterns:
>
> Done
>
> gcc/ChangeLog:
>
> 2020-11-13 Joel Hutton <joel.hut...@arm.com>
>
> * config/aarch64/aarch64-simd.md: New patterns
> vec_widen_saddl_lo/hi_<mode>.
>
> From c52fd11f5d471200c1292fad3bc04056e7721f06 Mon Sep 17 00:00:00 2001
> From: Joel Hutton <joel.hut...@arm.com>
> Date: Mon, 9 Nov 2020 15:35:57 +0000
> Subject: [PATCH 1/3] [aarch64] Add vec_widen patterns to aarch64
>
> Add widening add and subtract patterns to the aarch64
> backend. These allow taking vectors of N elements of size S
> and performing and add/subtract on the high or low half
> widening the resulting elements and storing N/2 elements of size 2*S.
> These correspond to the addl,addl2,subl,subl2 instructions.
> ---
> gcc/config/aarch64/aarch64-simd.md | 47 ++++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/gcc/config/aarch64/aarch64-simd.md
> b/gcc/config/aarch64/aarch64-simd.md
> index 2cf6fe9154a..30299610635 100644
> --- a/gcc/config/aarch64/aarch64-simd.md
> +++ b/gcc/config/aarch64/aarch64-simd.md
> @@ -3382,6 +3382,53 @@
> [(set_attr "type" "neon_<ADDSUB:optab>_long")]
> )
>
> +(define_expand "vec_widen_<su>addl_lo_<mode>"
> + [(match_operand:<VWIDE> 0 "register_operand")
> + (ANY_EXTEND:<VWIDE> (match_operand:VQW 1 "register_operand"))
> + (ANY_EXTEND:<VWIDE> (match_operand:VQW 2 "register_operand"))]
> + "TARGET_SIMD"
> +{
> + rtx p = aarch64_simd_vect_par_cnst_half (<MODE>mode, <nunits>, false);
> + emit_insn (gen_aarch64_<su>addl<mode>_lo_internal (operands[0],
> operands[1],
> + operands[2], p));
Nit: operands[2] should be indented three more columns now that “s” and
“u” have changed to “<su>”.
OK with that change, thanks.
Richard
