On 7/17/20 4:32 PM, Segher Boessenkool wrote:
> Well, just make an "isa" value of "p9"?  Then you can just do
> 
> (define_insn "trunctdsd2"
>   [(set (match_operand:SD 0 "gpc_reg_operand" "=d")
>         (float_truncate:SD (match_operand:TD 1 "gpc_reg_operand" "d")))
>    (clobber (match_scratch:TD 2 "=&d"))
>    (clobber (match_scratch:DF 3 "=&d"))]
>   "TARGET_DFP"
>   "@
>    mffscdrni %3,7\;drdpq %2,%1\;mffscdrn %3,%3\;drsp %0,%2
>    mffs %3\;mtfsfi 7,7,1\;drdpq %2,%1\;mtfsf 0xff,%3,1,0\;drsp %0,%2"
>   [(set_attr "type" "dfp")
>    (set_attr "isa" "p9,*")
>    (set_attr "length" "16,20")])

As we discussed offline, we need the duplicated constraint alternatives
like below.  I'll test this and commit this if clean with the following
additional ChangeLog entry for the p9 addition.  Thanks.

        * config/rs6000/rs6000.md (define_attr "isa"): Add p9.
        (define_attr "enabled"): Handle p9.


Peter



diff --git a/gcc/config/rs6000/dfp.md b/gcc/config/rs6000/dfp.md
index e91d6f581ed..8f822732bac 100644
--- a/gcc/config/rs6000/dfp.md
+++ b/gcc/config/rs6000/dfp.md
@@ -155,6 +155,19 @@
   [(set_attr "type" "dfp")
    (set_attr "length" "8")])
 
+(define_insn "trunctdsd2"
+  [(set (match_operand:SD 0 "gpc_reg_operand" "=d,d")
+       (float_truncate:SD (match_operand:TD 1 "gpc_reg_operand" "d,d")))
+   (clobber (match_scratch:TD 2 "=&d,&d"))
+   (clobber (match_scratch:DF 3 "=&d,&d"))]
+  "TARGET_DFP"
+  "@
+   mffscdrni %3,7\;drdpq %2,%1\;mffscdrn %3,%3\;drsp %0,%2
+   mffs %3\;mtfsfi 7,7,1\;drdpq %2,%1\;mtfsf 0xff,%3,1,0\;drsp %0,%2"
+  [(set_attr "type" "dfp")
+   (set_attr "isa" "p9,*")
+   (set_attr "length" "16,20")])
+
 (define_insn "add<mode>3"
   [(set (match_operand:DDTD 0 "gpc_reg_operand" "=d")
        (plus:DDTD (match_operand:DDTD 1 "gpc_reg_operand" "%d")
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c0d9877c715..b3fcb845a38 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -322,7 +322,7 @@
   (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
 
 ;; The ISA we implement.
-(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9v,p9kf,p9tf,p10"
+(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10"
   (const_string "any"))
 
 ;; Is this alternative enabled for the current CPU/ISA/etc.?
@@ -351,6 +351,10 @@
          (match_test "TARGET_P8_VECTOR"))
      (const_int 1)
 
+     (and (eq_attr "isa" "p9")
+         (match_test "TARGET_MODULO"))
+     (const_int 1)
+
      (and (eq_attr "isa" "p9v")
          (match_test "TARGET_P9_VECTOR"))
      (const_int 1)

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