Bug report this patch fixes: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=87455

The patch is a trivial one-liner, so I believe there should be no need
to sign the CLA?

Copy of the patch is attached, because google cannot be trusted to not
munge whitespace.


>From c0a466dd626aafa5b58c6c9d43d50a1dbc005434 Mon Sep 17 00:00:00 2001
From: Fanael Linithien <fana...@gmail.com>
Date: Fri, 8 May 2020 19:02:26 +0200
Subject: [PATCH] Disable X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL on Zen
 [PR87455]

This tune control is actually suboptimal on Zen, because it introduces
unnecessary domain-crossing latency.

2020-05-08  Fanael Linithien  <fana...@gmail.com>

    PR target/87455
    * config/i386/x86-tune.def (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL):
    Disable for m_ZNVER.
---
 gcc/config/i386/x86-tune.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index 1776aba2d..a2514f357 100644
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -376,7 +376,7 @@ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL,
"sse_unaligned_store_optimal",
 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
    precision 128bit instructions instead of double where possible.   */
 DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL,
"sse_packed_single_insn_optimal",
-      m_BDVER | m_ZNVER)
+      m_BDVER)

 /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores.   */
 DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
-- 
2.26.2
From c0a466dd626aafa5b58c6c9d43d50a1dbc005434 Mon Sep 17 00:00:00 2001
From: Fanael Linithien <fana...@gmail.com>
Date: Fri, 8 May 2020 19:02:26 +0200
Subject: [PATCH] Disable X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL on Zen
 [PR87455]

This tune control is actually suboptimal on Zen, because it introduces
unnecessary domain-crossing latency.

2020-05-08  Fanael Linithien  <fana...@gmail.com>

	PR target/87455
	* config/i386/x86-tune.def (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL):
	Disable for m_ZNVER.
---
 gcc/config/i386/x86-tune.def | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def
index 1776aba2d..a2514f357 100644
--- a/gcc/config/i386/x86-tune.def
+++ b/gcc/config/i386/x86-tune.def
@@ -376,7 +376,7 @@ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
 /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
    precision 128bit instructions instead of double where possible.   */
 DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
-	  m_BDVER | m_ZNVER)
+	  m_BDVER)
 
 /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores.   */
 DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
-- 
2.26.2

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