Hello Kyrill,
Following patch is the rebased version of v1.
(version v1) https://gcc.gnu.org/pipermail/gcc-patches/2019-November/534342.html
####
Hello,
This patch supports following MVE ACLE intrinsics with unary operand.
vctp16q, vctp32q, vctp64q, vctp8q, vpnot.
Please refer to M-profile Vector Extension (MVE) intrinsics [1] for more
details.
[1]
https://developer.arm.com/architectures/instruction-sets/simd-isas/helium/mve-intrinsics
There are few conflicts in defining the machine registers, resolved by
re-ordering
VPR_REGNUM, APSRQ_REGNUM and APSRGE_REGNUM.
Regression tested on target arm-none-eabi and armeb-none-eabi and found no
regressions.
Ok for trunk?
Thanks,
Srinath.
gcc/ChangeLog:
2020-03-06 Andre Vieira <andre.simoesdiasvie...@arm.com>
Mihail Ionescu <mihail.ione...@arm.com>
Srinath Parvathaneni <srinath.parvathan...@arm.com>
* config/arm/arm-builtins.c (hi_UP): Define mode.
* config/arm/arm.h (IS_VPR_REGNUM): Move.
* config/arm/arm.md (VPR_REGNUM): Define before APSRQ_REGNUM.
(APSRQ_REGNUM): Modify.
(APSRGE_REGNUM): Modify.
* config/arm/arm_mve.h (vctp16q): Define macro.
(vctp32q): Likewise.
(vctp64q): Likewise.
(vctp8q): Likewise.
(vpnot): Likewise.
(__arm_vctp16q): Define intrinsic.
(__arm_vctp32q): Likewise.
(__arm_vctp64q): Likewise.
(__arm_vctp8q): Likewise.
(__arm_vpnot): Likewise.
* config/arm/arm_mve_builtins.def (UNOP_UNONE_UNONE): Use builtin
qualifier.
* config/arm/mve.md (mve_vctp<mode1>qhi): Define RTL pattern.
(mve_vpnothi): Likewise.
gcc/testsuite/ChangeLog:
2020-03-06 Andre Vieira <andre.simoesdiasvie...@arm.com>
Mihail Ionescu <mihail.ione...@arm.com>
Srinath Parvathaneni <srinath.parvathan...@arm.com>
* gcc.target/arm/mve/intrinsics/vctp16q.c: New test.
* gcc.target/arm/mve/intrinsics/vctp32q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp64q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vctp8q.c: Likewise.
* gcc.target/arm/mve/intrinsics/vpnot.c: Likewise.
############### Attachment also inlined for ease of reply ###############
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index
0d5da5ea3133ca39b55b4ca76507e01956997c03..fd449458bcb1f9a899a16e432aa015d48b665868
100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -415,6 +415,7 @@ arm_set_sat_qualifiers[SIMD_MAX_BUILTIN_ARGS]
#define hf_UP E_HFmode
#define bf_UP E_BFmode
#define si_UP E_SImode
+#define hi_UP E_HImode
#define void_UP E_VOIDmode
#define sf_UP E_SFmode
#define UP(X) X##_UP
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index
912849f0acd36e9c8c3a00f4253a691b7085e72d..7f94e11c0ea23dfbdb7e64fafbdfc68d83411865
100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -192,6 +192,11 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
#define vcvtmq_u32_f32(__a) __arm_vcvtmq_u32_f32(__a)
#define vcvtaq_u16_f16(__a) __arm_vcvtaq_u16_f16(__a)
#define vcvtaq_u32_f32(__a) __arm_vcvtaq_u32_f32(__a)
+#define vctp16q(__a) __arm_vctp16q(__a)
+#define vctp32q(__a) __arm_vctp32q(__a)
+#define vctp64q(__a) __arm_vctp64q(__a)
+#define vctp8q(__a) __arm_vctp8q(__a)
+#define vpnot(__a) __arm_vpnot(__a)
#endif
__extension__ extern __inline void
@@ -703,6 +708,41 @@ __arm_vaddlvq_u32 (uint32x4_t __a)
return __builtin_mve_vaddlvq_uv4si (__a);
}
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vctp16q (uint32_t __a)
+{
+ return __builtin_mve_vctp16qhi (__a);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vctp32q (uint32_t __a)
+{
+ return __builtin_mve_vctp32qhi (__a);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vctp64q (uint32_t __a)
+{
+ return __builtin_mve_vctp64qhi (__a);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vctp8q (uint32_t __a)
+{
+ return __builtin_mve_vctp8qhi (__a);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vpnot (mve_pred16_t __a)
+{
+ return __builtin_mve_vpnothi (__a);
+}
+
#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
__extension__ extern __inline void
diff --git a/gcc/config/arm/arm_mve_builtins.def
b/gcc/config/arm/arm_mve_builtins.def
index
44807d6e8c4a4717c4f2fd2ef7015708ca3af4bc..5d5696965457e4fe138c194d7f3c3c5737bf68d0
100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -71,3 +71,8 @@ VAR2 (UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si)
VAR2 (UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si)
VAR1 (UNOP_UNONE_UNONE, vrev16q_u, v16qi)
VAR1 (UNOP_UNONE_UNONE, vaddlvq_u, v4si)
+VAR1 (UNOP_UNONE_UNONE, vctp16q, hi)
+VAR1 (UNOP_UNONE_UNONE, vctp32q, hi)
+VAR1 (UNOP_UNONE_UNONE, vctp64q, hi)
+VAR1 (UNOP_UNONE_UNONE, vctp8q, hi)
+VAR1 (UNOP_UNONE_UNONE, vpnot, hi)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index
dafdc1cf16e8ef51e39e8df1670fe29caa86d8e4..2f997e8f80b41d7e9f173c54bf4fd5854e2d8c24
100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -36,7 +36,7 @@
VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S
VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S
VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
- VADDLVQ_U])
+ VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT])
(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
(V8HF "V8HI") (V4SF "V4SI")])
@@ -54,6 +54,9 @@
(VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
(VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")])
+(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
+ (VCTP64Q "64")])
+
(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
(define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
(define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
@@ -71,6 +74,7 @@
(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
+(define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
(define_insn "*mve_mov<mode>"
[(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
@@ -655,3 +659,31 @@
"vaddlv.<supf>32 %Q0, %R0, %q1"
[(set_attr "type" "mve_move")
])
+
+;;
+;; [vctp8q vctp16q vctp32q vctp64q])
+;;
+(define_insn "mve_vctp<mode1>qhi"
+ [
+ (set (match_operand:HI 0 "vpr_register_operand" "=Up")
+ (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")]
+ VCTPQ))
+ ]
+ "TARGET_HAVE_MVE"
+ "vctp.<mode1> %1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vpnot])
+;;
+(define_insn "mve_vpnothi"
+ [
+ (set (match_operand:HI 0 "vpr_register_operand" "=Up")
+ (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")]
+ VPNOT))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpnot"
+ [(set_attr "type" "mve_move")
+])
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
new file mode 100644
index
0000000000000000000000000000000000000000..52a6b52725f9cc6ac9c8249847001b1d824142fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (uint32_t a)
+{
+ return vctp16q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.16" } } */
+
+mve_pred16_t
+foo1 (uint32_t a)
+{
+ return vctp16q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
new file mode 100644
index
0000000000000000000000000000000000000000..703518a4d9cca6a1553eb84bee6f382b99de022c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (uint32_t a)
+{
+ return vctp32q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.32" } } */
+
+mve_pred16_t
+foo1 (uint32_t a)
+{
+ return vctp32q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
new file mode 100644
index
0000000000000000000000000000000000000000..2f83a2249eed51b4ef2b9d12da9171eced8e0b41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (uint32_t a)
+{
+ return vctp64q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.64" } } */
+
+mve_pred16_t
+foo1 (uint32_t a)
+{
+ return vctp64q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.64" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
new file mode 100644
index
0000000000000000000000000000000000000000..ed696ac86e68ade93e2d741dd8eab72122046901
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (uint32_t a)
+{
+ return vctp8q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.8" } } */
+
+mve_pred16_t
+foo1 (uint32_t a)
+{
+ return vctp8q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
new file mode 100644
index
0000000000000000000000000000000000000000..7e08b1b90fe124881b17f5e7ab5690375a253bd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (mve_pred16_t a)
+{
+ return vpnot (a);
+}
+
+/* { dg-final { scan-assembler "vpnot" } } */
+
+mve_pred16_t
+foo1 (mve_pred16_t a)
+{
+ return vpnot (a);
+}
+
+/* { dg-final { scan-assembler "vpnot" } } */
diff --git a/gcc/config/arm/arm-builtins.c b/gcc/config/arm/arm-builtins.c
index
0d5da5ea3133ca39b55b4ca76507e01956997c03..fd449458bcb1f9a899a16e432aa015d48b665868
100644
--- a/gcc/config/arm/arm-builtins.c
+++ b/gcc/config/arm/arm-builtins.c
@@ -415,6 +415,7 @@ arm_set_sat_qualifiers[SIMD_MAX_BUILTIN_ARGS]
#define hf_UP E_HFmode
#define bf_UP E_BFmode
#define si_UP E_SImode
+#define hi_UP E_HImode
#define void_UP E_VOIDmode
#define sf_UP E_SFmode
#define UP(X) X##_UP
diff --git a/gcc/config/arm/arm_mve.h b/gcc/config/arm/arm_mve.h
index
912849f0acd36e9c8c3a00f4253a691b7085e72d..7f94e11c0ea23dfbdb7e64fafbdfc68d83411865
100644
--- a/gcc/config/arm/arm_mve.h
+++ b/gcc/config/arm/arm_mve.h
@@ -192,6 +192,11 @@ typedef struct { uint8x16_t val[4]; } uint8x16x4_t;
#define vcvtmq_u32_f32(__a) __arm_vcvtmq_u32_f32(__a)
#define vcvtaq_u16_f16(__a) __arm_vcvtaq_u16_f16(__a)
#define vcvtaq_u32_f32(__a) __arm_vcvtaq_u32_f32(__a)
+#define vctp16q(__a) __arm_vctp16q(__a)
+#define vctp32q(__a) __arm_vctp32q(__a)
+#define vctp64q(__a) __arm_vctp64q(__a)
+#define vctp8q(__a) __arm_vctp8q(__a)
+#define vpnot(__a) __arm_vpnot(__a)
#endif
__extension__ extern __inline void
@@ -703,6 +708,41 @@ __arm_vaddlvq_u32 (uint32x4_t __a)
return __builtin_mve_vaddlvq_uv4si (__a);
}
+__extension__ extern __inline int64_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vctp16q (uint32_t __a)
+{
+ return __builtin_mve_vctp16qhi (__a);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vctp32q (uint32_t __a)
+{
+ return __builtin_mve_vctp32qhi (__a);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vctp64q (uint32_t __a)
+{
+ return __builtin_mve_vctp64qhi (__a);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vctp8q (uint32_t __a)
+{
+ return __builtin_mve_vctp8qhi (__a);
+}
+
+__extension__ extern __inline mve_pred16_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+__arm_vpnot (mve_pred16_t __a)
+{
+ return __builtin_mve_vpnothi (__a);
+}
+
#if (__ARM_FEATURE_MVE & 2) /* MVE Floating point. */
__extension__ extern __inline void
diff --git a/gcc/config/arm/arm_mve_builtins.def
b/gcc/config/arm/arm_mve_builtins.def
index
44807d6e8c4a4717c4f2fd2ef7015708ca3af4bc..5d5696965457e4fe138c194d7f3c3c5737bf68d0
100644
--- a/gcc/config/arm/arm_mve_builtins.def
+++ b/gcc/config/arm/arm_mve_builtins.def
@@ -71,3 +71,8 @@ VAR2 (UNOP_UNONE_NONE, vcvtaq_u, v8hi, v4si)
VAR2 (UNOP_UNONE_IMM, vmvnq_n_u, v8hi, v4si)
VAR1 (UNOP_UNONE_UNONE, vrev16q_u, v16qi)
VAR1 (UNOP_UNONE_UNONE, vaddlvq_u, v4si)
+VAR1 (UNOP_UNONE_UNONE, vctp16q, hi)
+VAR1 (UNOP_UNONE_UNONE, vctp32q, hi)
+VAR1 (UNOP_UNONE_UNONE, vctp64q, hi)
+VAR1 (UNOP_UNONE_UNONE, vctp8q, hi)
+VAR1 (UNOP_UNONE_UNONE, vpnot, hi)
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index
dafdc1cf16e8ef51e39e8df1670fe29caa86d8e4..2f997e8f80b41d7e9f173c54bf4fd5854e2d8c24
100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -36,7 +36,7 @@
VREV32Q_U VREV32Q_S VMOVLTQ_U VMOVLTQ_S VMOVLBQ_S
VMOVLBQ_U VCVTQ_FROM_F_S VCVTQ_FROM_F_U VCVTPQ_S
VCVTPQ_U VCVTNQ_S VCVTNQ_U VCVTMQ_S VCVTMQ_U
- VADDLVQ_U])
+ VADDLVQ_U VCTP8Q VCTP16Q VCTP32Q VCTP64Q VPNOT])
(define_mode_attr MVE_CNVT [(V8HI "V8HF") (V4SI "V4SF")
(V8HF "V8HI") (V4SF "V4SI")])
@@ -54,6 +54,9 @@
(VCLZQ_U "u") (VCLZQ_S "s") (VREV32Q_U "u")
(VREV32Q_S "s") (VADDLVQ_U "u") (VADDLVQ_S "s")])
+(define_int_attr mode1 [(VCTP8Q "8") (VCTP16Q "16") (VCTP32Q "32")
+ (VCTP64Q "64")])
+
(define_int_iterator VCVTQ_TO_F [VCVTQ_TO_F_S VCVTQ_TO_F_U])
(define_int_iterator VMVNQ_N [VMVNQ_N_U VMVNQ_N_S])
(define_int_iterator VREV64Q [VREV64Q_S VREV64Q_U])
@@ -71,6 +74,7 @@
(define_int_iterator VCVTNQ [VCVTNQ_S VCVTNQ_U])
(define_int_iterator VCVTMQ [VCVTMQ_S VCVTMQ_U])
(define_int_iterator VADDLVQ [VADDLVQ_U VADDLVQ_S])
+(define_int_iterator VCTPQ [VCTP8Q VCTP16Q VCTP32Q VCTP64Q])
(define_insn "*mve_mov<mode>"
[(set (match_operand:MVE_types 0 "nonimmediate_operand" "=w,w,r,w,w,r,w,Us")
@@ -655,3 +659,31 @@
"vaddlv.<supf>32 %Q0, %R0, %q1"
[(set_attr "type" "mve_move")
])
+
+;;
+;; [vctp8q vctp16q vctp32q vctp64q])
+;;
+(define_insn "mve_vctp<mode1>qhi"
+ [
+ (set (match_operand:HI 0 "vpr_register_operand" "=Up")
+ (unspec:HI [(match_operand:SI 1 "s_register_operand" "r")]
+ VCTPQ))
+ ]
+ "TARGET_HAVE_MVE"
+ "vctp.<mode1> %1"
+ [(set_attr "type" "mve_move")
+])
+
+;;
+;; [vpnot])
+;;
+(define_insn "mve_vpnothi"
+ [
+ (set (match_operand:HI 0 "vpr_register_operand" "=Up")
+ (unspec:HI [(match_operand:HI 1 "vpr_register_operand" "0")]
+ VPNOT))
+ ]
+ "TARGET_HAVE_MVE"
+ "vpnot"
+ [(set_attr "type" "mve_move")
+])
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
new file mode 100644
index
0000000000000000000000000000000000000000..52a6b52725f9cc6ac9c8249847001b1d824142fe
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (uint32_t a)
+{
+ return vctp16q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.16" } } */
+
+mve_pred16_t
+foo1 (uint32_t a)
+{
+ return vctp16q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.16" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
new file mode 100644
index
0000000000000000000000000000000000000000..703518a4d9cca6a1553eb84bee6f382b99de022c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (uint32_t a)
+{
+ return vctp32q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.32" } } */
+
+mve_pred16_t
+foo1 (uint32_t a)
+{
+ return vctp32q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.32" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
new file mode 100644
index
0000000000000000000000000000000000000000..2f83a2249eed51b4ef2b9d12da9171eced8e0b41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (uint32_t a)
+{
+ return vctp64q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.64" } } */
+
+mve_pred16_t
+foo1 (uint32_t a)
+{
+ return vctp64q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.64" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
new file mode 100644
index
0000000000000000000000000000000000000000..ed696ac86e68ade93e2d741dd8eab72122046901
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (uint32_t a)
+{
+ return vctp8q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.8" } } */
+
+mve_pred16_t
+foo1 (uint32_t a)
+{
+ return vctp8q (a);
+}
+
+/* { dg-final { scan-assembler "vctp.8" } } */
diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
new file mode 100644
index
0000000000000000000000000000000000000000..7e08b1b90fe124881b17f5e7ab5690375a253bd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vpnot.c
@@ -0,0 +1,22 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O2" } */
+
+#include "arm_mve.h"
+
+mve_pred16_t
+foo (mve_pred16_t a)
+{
+ return vpnot (a);
+}
+
+/* { dg-final { scan-assembler "vpnot" } } */
+
+mve_pred16_t
+foo1 (mve_pred16_t a)
+{
+ return vpnot (a);
+}
+
+/* { dg-final { scan-assembler "vpnot" } } */
