On 2/27/20 9:30 AM, Jakub Jelinek wrote:
On Thu, Feb 27, 2020 at 09:19:25AM -0600, Bill Schmidt wrote:
On 2/27/20 8:52 AM, Jakub Jelinek wrote:
On Thu, Feb 27, 2020 at 08:47:19AM -0600, Bill Schmidt wrote:
But is this actually a good idea? It seems to me this will generate lousy
code in the absence of hardware support. Won't we be better off warning and
ignoring the directive, leaving the code in scalar form?
Depends on the exact code, I think sometimes it will be just fine and will
allow vectorizing something that really couldn't be otherwise.
Isn't it better to leave it for the user to decide?
They can always ask for it not to be generated (add notinbranch) if it isn't
worthwhile.
You need a high ratio of unguarded code to guarded code in order to pay for all
those vector extract and reconstruct operations. Sure, some code will be fine,
but a lot of code will be lousy. This will be particularly true on older
hardware with a less exhaustive set of vector operations.
Why? E.g. for integral code other than division or memory loads/stores where
nothing will really trap, you can just perform it unguarded.
Just use whatever the vectorizer does right now for conditional code, and if
that isn't as efficient as it could be given a particular HW/ISA, try to improve
it?
If that's how the vectorizer is working today, then my concerns are certainly
lessened. It's been a while since I've seen how the vectorizer and
if-conversion
interact, so my perspective is probably outdated. We'll take a look at it.
Thanks for the discussion!
Bill
I really don't see how is it different say from SSE2 on x86 or even AVX.
Jakub
