On Wed, Feb 26, 2020 at 04:09:16PM +0800, luoxhu wrote:
> Thanks Richard, not sure about my understanding and please correct if any.
>
> I tried Jukub's latest patch of "sccvn: Handle bitfields in push_partial_def".
> Got to know fre pass checks the load instruction's vuse chain and do the
> constant
> bitfield combines in push_partial_def, then
> native_encode_expr/native_interpret_expr
> can decode and encode the constant content and shift/combine the data.
> This should be based on one change to my test case(by adding return
> page->counters;)
> to trigger the fre pass push all SSA name's partial_defs. Currently, for SSA
> variables,
> this encode/interpret is not supported yet, I suppose this is the opportunity
> you mean.
> As this case's input is not constant, so Jukub's patch doesn't fix it.
Yeah, I've looked at your case and the problem is that
tmp.counters = counters_new;
page->inuse = tmp.inuse;
page->inuse2 = tmp.inuse2;
page->objects = tmp.objects;
page->frozen = tmp.frozen;
we optimize it into essentially:
tmp.counters = counters_new;
page->inuse = (cast) counters_new;
page->inuse2 = tmp.inuse2;
page->objects = tmp.objects;
page->frozen = tmp.frozen;
and so it is no longer recognized as a mem copy. What we could do is just
teach store-merging to virtually undo that optimization and consider the
store to be a MEM_REF too. Especially for the BIT_INSERT_EXPR Eric has
added quite a few similar optimizations already.
Jakub
