[PATCH 07/10] i386: Use ix86_output_ssemov for TFmode TYPE_SSEMOV

[H.J. Lu]

gcc/

        PR target/89229
        * config/i386/i386.md (*movtf_internal): Call ix86_output_ssemov
        for TYPE_SSEMOV.

gcc/testsuite/

        PR target/89229
        * gcc.target/i386/pr89229-5a.c: New test.
        * gcc.target/i386/pr89229-5b.c: Likewise.
        * gcc.target/i386/pr89229-5c.c: Likewise.
---
 gcc/config/i386/i386.md                    | 26 +---------------------
 gcc/testsuite/gcc.target/i386/pr89229-5a.c | 16 +++++++++++++
 gcc/testsuite/gcc.target/i386/pr89229-5b.c | 12 ++++++++++
 gcc/testsuite/gcc.target/i386/pr89229-5c.c |  6 +++++
 4 files changed, 35 insertions(+), 25 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-5a.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-5b.c
 create mode 100644 gcc/testsuite/gcc.target/i386/pr89229-5c.c

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 05815c5cf3b..fdf0e5a8802 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -3154,31 +3154,7 @@ (define_insn "*movtf_internal"
       return standard_sse_constant_opcode (insn, operands);
 
     case TYPE_SSEMOV:
-      /* Handle misaligned load/store since we
-         don't have movmisaligntf pattern. */
-      if (misaligned_operand (operands[0], TFmode)
-         || misaligned_operand (operands[1], TFmode))
-       {
-         if (get_attr_mode (insn) == MODE_V4SF)
-           return "%vmovups\t{%1, %0|%0, %1}";
-         else if (TARGET_AVX512VL
-                  && (EXT_REX_SSE_REG_P (operands[0])
-                      || EXT_REX_SSE_REG_P (operands[1])))
-           return "vmovdqu64\t{%1, %0|%0, %1}";
-         else
-           return "%vmovdqu\t{%1, %0|%0, %1}";
-       }
-      else
-       {
-         if (get_attr_mode (insn) == MODE_V4SF)
-           return "%vmovaps\t{%1, %0|%0, %1}";
-         else if (TARGET_AVX512VL
-                  && (EXT_REX_SSE_REG_P (operands[0])
-                      || EXT_REX_SSE_REG_P (operands[1])))
-           return "vmovdqa64\t{%1, %0|%0, %1}";
-         else
-           return "%vmovdqa\t{%1, %0|%0, %1}";
-       }
+      return ix86_output_ssemov (insn, operands);
 
     case TYPE_MULTI:
        return "#";
diff --git a/gcc/testsuite/gcc.target/i386/pr89229-5a.c 
b/gcc/testsuite/gcc.target/i386/pr89229-5a.c
new file mode 100644
index 00000000000..fcb85c366b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-5a.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512" } */
+
+extern __float128 d;
+
+void
+foo1 (__float128 x)
+{
+  register __float128 xmm16 __asm ("xmm16") = x;
+  asm volatile ("" : "+v" (xmm16));
+  register __float128 xmm17 __asm ("xmm17") = xmm16;
+  asm volatile ("" : "+v" (xmm17));
+  d = xmm17;
+}
+
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
diff --git a/gcc/testsuite/gcc.target/i386/pr89229-5b.c 
b/gcc/testsuite/gcc.target/i386/pr89229-5b.c
new file mode 100644
index 00000000000..37eb83c783b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-5b.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512 -mno-avx512vl" } */
+
+extern __float128 d;
+
+void
+foo1 (__float128 x)
+{
+  register __float128 xmm16 __asm ("xmm16") = x; /* { dg-error "register 
specified for 'xmm16'" } */
+  asm volatile ("" : "+v" (xmm16));
+  d = xmm16;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr89229-5c.c 
b/gcc/testsuite/gcc.target/i386/pr89229-5c.c
new file mode 100644
index 00000000000..529a520133c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89229-5c.c
@@ -0,0 +1,6 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -march=skylake-avx512 -mprefer-vector-width=512" } */
+
+#include "pr89229-5a.c"
+
+/* { dg-final { scan-assembler-not "%zmm\[0-9\]+" } } */
-- 
2.24.1