[committed, amdgcn] Use V64SI for all remaining add-with-carry insns

[Andrew Stubbs]

This patch does nothing but replace a mode iterator with the concrete 
mode. It has no effect on the generated machine description whatsoever.

This is part of an incremental clean-up of the mode iterators, following 
the introduction of vector QI/HI support. The add-with-carry 
instructions are not interesting for those modes (being mostly used to 
implement DImode splitters), so we can dispense with the notional iterator.

Andrew
Use V64SI for all amdgcn add-with-carry insns

2019-12-19  Andrew Stubbs  <a...@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (*plus_carry_dpp_shr_<mode>): Rename to ...
	(*plus_carry_dpp_shr_v64si): ... this, and replace all
	VEC_1REG_INT_MODE with V64SI.

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 00a7604d686..369aae5bfc5 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -3075,18 +3075,18 @@
 
 ; Special cases for addition.
 
-(define_insn "*plus_carry_dpp_shr_<mode>"
-  [(set (match_operand:VEC_1REG_INT_MODE 0 "register_operand"   "=v")
-	(unspec:VEC_1REG_INT_MODE
-	  [(match_operand:VEC_1REG_INT_MODE 1 "register_operand" "v")
-	   (match_operand:VEC_1REG_INT_MODE 2 "register_operand" "v")
-	   (match_operand:SI 3 "const_int_operand"		 "n")]
+(define_insn "*plus_carry_dpp_shr_v64si"
+  [(set (match_operand:V64SI 0 "register_operand"   "=v")
+	(unspec:V64SI
+	  [(match_operand:V64SI 1 "register_operand" "v")
+	   (match_operand:V64SI 2 "register_operand" "v")
+	   (match_operand:SI 3 "const_int_operand"   "n")]
 	  UNSPEC_PLUS_CARRY_DPP_SHR))
    (clobber (reg:DI VCC_REG))]
   ""
   {
     const char *insn = TARGET_GCN3 ? "v_add%u0" : "v_add_co%u0";
-    return gcn_expand_dpp_shr_insn (<MODE>mode, insn,
+    return gcn_expand_dpp_shr_insn (V64SImode, insn,
 				    UNSPEC_PLUS_CARRY_DPP_SHR,
 				    INTVAL (operands[3]));
   }