"Richard Earnshaw (lists)" <richard.earns...@arm.com> writes:
> On 17/09/2019 15:57, Richard Sandiford wrote:
>> no_insn is documented as:
>>
>> an insn which does not represent an instruction in the final output,
>> thus having no impact on scheduling.
>>
>> and is used in that way by the arm port (e.g. for define_insns that
>> expand to comments). However, most scheduling descriptions instead
>> assigned units to no_insn patterns, in some cases treating them as more
>> expensive than a plain move.
>>
>> This patch removes the no_insn handling from individual scheduling
>> descriptions and uses a common define_insn_reservation for all CPUs.
>>
>> Tested on aarch64-linux-gnu and armeab-none-eabi. OK to install?
>>
>
> OK.
>
> Out of interest, does this affect the number of atomata states
> significantly?
No, it's a very minor improvement, but not one we'll notice:
@@ -5,7 +5,7 @@
15 minimal DFA states, 113 minimal DFA arcs
629 all insns 14 insn equivalence classes
0 locked states
- 145 transition comb vector els, 210 trans table els: use simple vect
+ 142 transition comb vector els, 210 trans table els: use simple vect
210 min delay table els, compression factor 4
Automaton `cortex_a53_advsimd'
@@ -243,7 +243,7 @@
35 min delay table els, compression factor 4
13689 all allocated states, 38825 all allocated arcs
-43554 all allocated alternative states
-45768 all transition comb vector els, 91862 all trans table els
+43473 all allocated alternative states
+45765 all transition comb vector els, 91862 all trans table els
91862 all min delay table els
0 all locked states
Thanks,
Richard
