Hi Eric, On Wed, Sep 11, 2019 at 12:39:51PM +0200, Eric Botcazou wrote: > This fixes a wrong code generation on the ARM in very peculiar circumstances > ( > -O2 -fno-dce -fno-forward-propagate -fno-sched-pressure) present on all > active > branches in the form of a missing zero-extension. It turns out that not all > parts of the RTL middle-end agree on the assumptions valid on RISC machines > as > encoded by WORD_REGISTER_OPERATIONS, so the nonzero_bits machinery needs to > be > more conservative with them. As witnessed by the added XFAIL, this will add > back some redundant zero-extensions on WORD_REGISTER_OPERATIONS targets.
But what are those assumptions, _exactly_? It's not clear to me. WORD_REGISTER_OPERATIONS Define this macro if operations between registers with integral mode smaller than a word are always performed on the entire register. Most RISC machines have this property and most CISC machines do not. What does it mean for (set (reg:QI) (const_int -128)) for example? This is the canonical form of moving positive 128 into a register as well, of course. On a target with 64-bit registers, does it mean that (set (reg:SI d) (mult:SI (reg:SI a) (reg:SI b))) is actually done as (set (reg:DI d) (mult:DI (reg:DI a) (reg:DI b))) ? I can't think of any hardware where that is true. W_R_O needs many more restrictions if it can work at all, but those aren't documented. Segher
