This fixes a wrong code generation on the ARM in very peculiar circumstances (
-O2 -fno-dce -fno-forward-propagate -fno-sched-pressure) present on all active
branches in the form of a missing zero-extension. It turns out that not all
parts of the RTL middle-end agree on the assumptions valid on RISC machines as
encoded by WORD_REGISTER_OPERATIONS, so the nonzero_bits machinery needs to be
more conservative with them. As witnessed by the added XFAIL, this will add
back some redundant zero-extensions on WORD_REGISTER_OPERATIONS targets.
Tested on SPARC/Solaris and SPARC64/Linux, applied on all active branches.
2019-09-11 Eric Botcazou <ebotca...@adacore.com>
PR rtl-optimization/89795
* rtlanal.c (nonzero_bits1) <SUBREG>: Do not propagate results from
inner REGs to paradoxical SUBREGs if WORD_REGISTER_OPERATIONS is set.
2019-09-11 Eric Botcazou <ebotca...@adacore.com>
* gcc.target/sparc/20161111-1.c: XFAIL redundant zero-extension test.
--
Eric BotcazouIndex: rtlanal.c
===================================================================
--- rtlanal.c (revision 275484)
+++ rtlanal.c (working copy)
@@ -4810,7 +4810,7 @@ nonzero_bits1 (const_rtx x, scalar_int_m
|| ((extend_op = load_extend_op (inner_mode)) == SIGN_EXTEND
? val_signbit_known_set_p (inner_mode, nonzero)
: extend_op != ZERO_EXTEND)
- || (!MEM_P (SUBREG_REG (x)) && !REG_P (SUBREG_REG (x))))
+ || !MEM_P (SUBREG_REG (x)))
&& xmode_width > inner_width)
nonzero
|= (GET_MODE_MASK (GET_MODE (x)) & ~GET_MODE_MASK (inner_mode));
Index: testsuite/gcc.target/sparc/20161111-1.c
===================================================================
--- testsuite/gcc.target/sparc/20161111-1.c (revision 275484)
+++ testsuite/gcc.target/sparc/20161111-1.c (working copy)
@@ -14,4 +14,4 @@ unsigned char ee_isdigit2(unsigned int i
return retval;
}
-/* { dg-final { scan-assembler-not "and\t%" } } */
+/* { dg-final { scan-assembler-not "and\t%" { xfail *-*-* } } } */
