On 11/24/2011 02:34 AM, Richard Earnshaw wrote: >> + unsigned long s[8]; /* r4-r12 */ > > R4-R12 is 9 registers. But R12 is callee clobbered. So is the code or > the comment incorrect?
The comment is clearly a typo. >> +/* ARM generally uses a fixed page size of 4K. */ >> +#define PAGE_SIZE 4096 >> +#define FIXED_PAGE_SIZE 1 > > So I know that on AArch64 there's some interest in moving to larger > pages than this in order to reduce the number of TLB walks needed; this > may impact on the ARM code as well, long term. > >> + >> +/* ??? The size of one line in hardware caches (in bytes). */ >> +#define HW_CACHELINE_SIZE 64 > > You can't assume this. It can vary per core (and I think it may even > vary depending on the cache level). We don't actually need perfectly accurate values for these. The only place that we use HW_CACHELINE_SIZE is an attempt to put shared data and thread private data in different lines to prevent ping ponging. r~
