On 23/11/11 23:47, Richard Henderson wrote:
> To get the ball rolling for other targets, and to let port maintainers see
> how easy it really is, here's a first cut at a port to ARM.
>
> Only cross-compiled as yet, and qemu-linux-user isn't good enough to emulate.
> I'll do another build on the armv7 host once my current bootstrap and test
> for the atomic optabs is complete.
>
> Please review, especially the local setjmp-alike implementation.
>
>
> r~
>
>
> d-arm-libitm
>
>
> + .text
> + .align 2
> + .global _ITM_beginTransaction
> + .type _ITM_beginTransaction, %function
> +
> +_ITM_beginTransaction:
> + push { r4-r11, sp, lr }
> + mov r1, sp
> + bl GTM_begin_transaction
What about systems with floating-point or vector registers? Ie VFP or
WMMX on XScale? Do the callee saved registers in those register banks
also have to be saved?
> diff --git a/libitm/config/arm/target.h b/libitm/config/arm/target.h
> + unsigned long s[8]; /* r4-r12 */
R4-R12 is 9 registers. But R12 is callee clobbered. So is the code or
the comment incorrect?
> +/* ARM generally uses a fixed page size of 4K. */
> +#define PAGE_SIZE 4096
> +#define FIXED_PAGE_SIZE 1
So I know that on AArch64 there's some interest in moving to larger
pages than this in order to reduce the number of TLB walks needed; this
may impact on the ARM code as well, long term.
> +
> +/* ??? The size of one line in hardware caches (in bytes). */
> +#define HW_CACHELINE_SIZE 64
You can't assume this. It can vary per core (and I think it may even
vary depending on the cache level).
> +
> +static inline void
> +cpu_relax (void)
> +{
> + /* ??? Maybe use WFE. */
Maybe, but WFE doesn't exist on older CPUs
> diff --git a/libitm/config/linux/arm/futex_bits.h
> b/libitm/config/linux/arm/futex_bits.h
As discussed elsewhere, better to use syscall here rather than try to
inline it.
R.
