On Fri, Jul 5, 2019 at 5:15 PM Richard Sandiford
<richard.sandif...@arm.com> wrote:
>
> This patch is part of a series that fixes ambiguous attribute
> uses in .md files, i.e. cases in which attributes didn't use
> <ITER:ATTR> to specify an iterator, and in which <ATTR> could
> have different values depending on the iterator chosen.
>
> No behavioural change except for dropping the unused *andnot<mode>3_bcst
> permutations.
>
>
> 2019-07-05 Richard Sandiford <richard.sandif...@arm.com>
>
> gcc/
> * config/i386/i386.md (*fop_<X87MODEF:mode>_3_i387)
> (l<rounding_insn><MODEF:mode><SWI48:mode>2): Fix ambiguous uses
> of .md attributes.
> * config/i386/sse.md (*avx512pf_gatherpf<mode>sf_mask)
> (*avx512pf_gatherpf<mode>df_mask, *avx512pf_scatterpf<mode>sf_mask)
> (*avx512pf_scatterpf<mode>df_mask, *avx2_gathersi<mode>)
> (*avx2_gathersi<mode>_2, *avx2_gatherdi<mode>)
> (*avx2_gatherdi<mode>_2, *avx2_gatherdi<mode>_3): Likewise.
> (*avx2_gatherdi<mode>_4, *avx512f_gathersi<mode>): Likewise.
> (*avx512f_gathersi<mode>_2, *avx512f_gatherdi<mode>): Likewise.
> (*avx512f_gatherdi<mode>_2, *avx512f_scattersi<mode>): Likewise.
> (*avx512f_scatterdi<mode>): Likewise.
> (*andnot<mode>3_bcst): Fix VI/VI48_AVX512VL typo.
OK.
Thanks,
Uros.
> Index: gcc/config/i386/i386.md
> ===================================================================
> --- gcc/config/i386/i386.md 2019-07-03 20:50:46.074319519 +0100
> +++ gcc/config/i386/i386.md 2019-07-05 15:05:55.216229452 +0100
> @@ -14755,7 +14755,7 @@ (define_insn "*fop_<X87MODEF:mode>_3_i38
> ]
> (const_string "fop")))
> (set_attr "fp_int_src" "true")
> - (set_attr "mode" "<MODE>")])
> + (set_attr "mode" "<SWI24:MODE>")])
>
> (define_insn "*fop_xf_4_i387"
> [(set (match_operand:XF 0 "register_operand" "=f,f")
> @@ -16457,7 +16457,7 @@ (define_expand "l<rounding_insn><MODEF:m
> {
> rtx tmp = gen_reg_rtx (<MODEF:MODE>mode);
>
> - emit_insn (gen_sse4_1_round<mode>2
> + emit_insn (gen_sse4_1_round<MODEF:mode>2
> (tmp, operands[1], GEN_INT (ROUND_<ROUNDING>
> | ROUND_NO_EXC)));
> emit_insn (gen_fix_trunc<MODEF:mode><SWI48:mode>2
> Index: gcc/config/i386/sse.md
> ===================================================================
> --- gcc/config/i386/sse.md 2019-07-03 20:50:46.078319486 +0100
> +++ gcc/config/i386/sse.md 2019-07-05 15:05:55.220229422 +0100
> @@ -12702,8 +12702,8 @@ (define_insn "*andnot<mode>3"
> (const_string "<sseinsnmode>")))])
>
> (define_insn "*andnot<mode>3_bcst"
> - [(set (match_operand:VI 0 "register_operand" "=v")
> - (and:VI
> + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
> + (and:VI48_AVX512VL
> (not:VI48_AVX512VL
> (match_operand:VI48_AVX512VL 1 "register_operand" "v"))
> (vec_duplicate:VI48_AVX512VL
> @@ -18085,7 +18085,7 @@ (define_expand "avx512pf_gatherpf<mode>s
> operands[3]), UNSPEC_VSIBADDR);
> })
>
> -(define_insn "*avx512pf_gatherpf<mode>sf_mask"
> +(define_insn "*avx512pf_gatherpf<VI48_512:mode>sf_mask"
> [(unspec
> [(match_operand:<avx512fmaskmode> 0 "register_operand" "Yk")
> (match_operator:<GATHER_SCATTER_SF_MEM_MODE> 5 "vsib_mem_operator"
> @@ -18132,7 +18132,7 @@ (define_expand "avx512pf_gatherpf<mode>d
> operands[3]), UNSPEC_VSIBADDR);
> })
>
> -(define_insn "*avx512pf_gatherpf<mode>df_mask"
> +(define_insn "*avx512pf_gatherpf<VI4_256_8_512:mode>df_mask"
> [(unspec
> [(match_operand:<avx512fmaskmode> 0 "register_operand" "Yk")
> (match_operator:V8DF 5 "vsib_mem_operator"
> @@ -18179,7 +18179,7 @@ (define_expand "avx512pf_scatterpf<mode>
> operands[3]), UNSPEC_VSIBADDR);
> })
>
> -(define_insn "*avx512pf_scatterpf<mode>sf_mask"
> +(define_insn "*avx512pf_scatterpf<VI48_512:mode>sf_mask"
> [(unspec
> [(match_operand:<avx512fmaskmode> 0 "register_operand" "Yk")
> (match_operator:<GATHER_SCATTER_SF_MEM_MODE> 5 "vsib_mem_operator"
> @@ -18228,7 +18228,7 @@ (define_expand "avx512pf_scatterpf<mode>
> operands[3]), UNSPEC_VSIBADDR);
> })
>
> -(define_insn "*avx512pf_scatterpf<mode>df_mask"
> +(define_insn "*avx512pf_scatterpf<VI4_256_8_512:mode>df_mask"
> [(unspec
> [(match_operand:<avx512fmaskmode> 0 "register_operand" "Yk")
> (match_operator:V8DF 5 "vsib_mem_operator"
> @@ -21017,7 +21017,7 @@ (define_expand "avx2_gathersi<mode>"
> operands[5]), UNSPEC_VSIBADDR);
> })
>
> -(define_insn "*avx2_gathersi<mode>"
> +(define_insn "*avx2_gathersi<VEC_GATHER_MODE:mode>"
> [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x")
> (unspec:VEC_GATHER_MODE
> [(match_operand:VEC_GATHER_MODE 2 "register_operand" "0")
> @@ -21037,7 +21037,7 @@ (define_insn "*avx2_gathersi<mode>"
> (set_attr "prefix" "vex")
> (set_attr "mode" "<sseinsnmode>")])
>
> -(define_insn "*avx2_gathersi<mode>_2"
> +(define_insn "*avx2_gathersi<VEC_GATHER_MODE:mode>_2"
> [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x")
> (unspec:VEC_GATHER_MODE
> [(pc)
> @@ -21078,7 +21078,7 @@ (define_expand "avx2_gatherdi<mode>"
> operands[5]), UNSPEC_VSIBADDR);
> })
>
> -(define_insn "*avx2_gatherdi<mode>"
> +(define_insn "*avx2_gatherdi<VEC_GATHER_MODE:mode>"
> [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x")
> (unspec:VEC_GATHER_MODE
> [(match_operand:<VEC_GATHER_SRCDI> 2 "register_operand" "0")
> @@ -21098,7 +21098,7 @@ (define_insn "*avx2_gatherdi<mode>"
> (set_attr "prefix" "vex")
> (set_attr "mode" "<sseinsnmode>")])
>
> -(define_insn "*avx2_gatherdi<mode>_2"
> +(define_insn "*avx2_gatherdi<VEC_GATHER_MODE:mode>_2"
> [(set (match_operand:VEC_GATHER_MODE 0 "register_operand" "=&x")
> (unspec:VEC_GATHER_MODE
> [(pc)
> @@ -21114,7 +21114,7 @@ (define_insn "*avx2_gatherdi<mode>_2"
> (clobber (match_scratch:VEC_GATHER_MODE 1 "=&x"))]
> "TARGET_AVX2"
> {
> - if (<MODE>mode != <VEC_GATHER_SRCDI>mode)
> + if (<VEC_GATHER_MODE:MODE>mode != <VEC_GATHER_SRCDI>mode)
> return "%M2v<sseintprefix>gatherq<ssemodesuffix>\t{%4, %6, %x0|%x0, %6,
> %4}";
> return "%M2v<sseintprefix>gatherq<ssemodesuffix>\t{%4, %6, %0|%0, %6, %4}";
> }
> @@ -21122,7 +21122,7 @@ (define_insn "*avx2_gatherdi<mode>_2"
> (set_attr "prefix" "vex")
> (set_attr "mode" "<sseinsnmode>")])
>
> -(define_insn "*avx2_gatherdi<mode>_3"
> +(define_insn "*avx2_gatherdi<VI4F_256:mode>_3"
> [(set (match_operand:<VEC_GATHER_SRCDI> 0 "register_operand" "=&x")
> (vec_select:<VEC_GATHER_SRCDI>
> (unspec:VI4F_256
> @@ -21145,7 +21145,7 @@ (define_insn "*avx2_gatherdi<mode>_3"
> (set_attr "prefix" "vex")
> (set_attr "mode" "<sseinsnmode>")])
>
> -(define_insn "*avx2_gatherdi<mode>_4"
> +(define_insn "*avx2_gatherdi<VI4F_256:mode>_4"
> [(set (match_operand:<VEC_GATHER_SRCDI> 0 "register_operand" "=&x")
> (vec_select:<VEC_GATHER_SRCDI>
> (unspec:VI4F_256
> @@ -21187,7 +21187,7 @@ (define_expand "<avx512>_gathersi<mode>"
> operands[5]), UNSPEC_VSIBADDR);
> })
>
> -(define_insn "*avx512f_gathersi<mode>"
> +(define_insn "*avx512f_gathersi<VI48F:mode>"
> [(set (match_operand:VI48F 0 "register_operand" "=&v")
> (unspec:VI48F
> [(match_operand:VI48F 1 "register_operand" "0")
> @@ -21208,7 +21208,7 @@ (define_insn "*avx512f_gathersi<mode>"
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
>
> -(define_insn "*avx512f_gathersi<mode>_2"
> +(define_insn "*avx512f_gathersi<VI48F:mode>_2"
> [(set (match_operand:VI48F 0 "register_operand" "=&v")
> (unspec:VI48F
> [(pc)
> @@ -21249,7 +21249,7 @@ (define_expand "<avx512>_gatherdi<mode>"
> operands[5]), UNSPEC_VSIBADDR);
> })
>
> -(define_insn "*avx512f_gatherdi<mode>"
> +(define_insn "*avx512f_gatherdi<VI48F:mode>"
> [(set (match_operand:VI48F 0 "register_operand" "=&v")
> (unspec:VI48F
> [(match_operand:<VEC_GATHER_SRCDI> 1 "register_operand" "0")
> @@ -21270,7 +21270,7 @@ (define_insn "*avx512f_gatherdi<mode>"
> (set_attr "prefix" "evex")
> (set_attr "mode" "<sseinsnmode>")])
>
> -(define_insn "*avx512f_gatherdi<mode>_2"
> +(define_insn "*avx512f_gatherdi<VI48F:mode>_2"
> [(set (match_operand:VI48F 0 "register_operand" "=&v")
> (unspec:VI48F
> [(pc)
> @@ -21287,9 +21287,9 @@ (define_insn "*avx512f_gatherdi<mode>_2"
> {
> /* %X5 so that we don't emit any *WORD PTR for -masm=intel, as
> gas changed what it requires incompatibly. */
> - if (<MODE>mode != <VEC_GATHER_SRCDI>mode)
> + if (<VI48F:MODE>mode != <VEC_GATHER_SRCDI>mode)
> {
> - if (<MODE_SIZE> != 64)
> + if (<VI48F:MODE_SIZE> != 64)
> return "%M3v<sseintprefix>gatherq<ssemodesuffix>\t{%5,
> %x0%{%1%}|%x0%{%1%}, %X5}";
> else
> return "%M3v<sseintprefix>gatherq<ssemodesuffix>\t{%5,
> %t0%{%1%}|%t0%{%1%}, %X5}";
> @@ -21318,7 +21318,7 @@ (define_expand "<avx512>_scattersi<mode>
> operands[4]), UNSPEC_VSIBADDR);
> })
>
> -(define_insn "*avx512f_scattersi<mode>"
> +(define_insn "*avx512f_scattersi<VI48F:mode>"
> [(set (match_operator:VI48F 5 "vsib_mem_operator"
> [(unspec:P
> [(match_operand:P 0 "vsib_address_operand" "Tv")
> @@ -21356,7 +21356,7 @@ (define_expand "<avx512>_scatterdi<mode>
> operands[4]), UNSPEC_VSIBADDR);
> })
>
> -(define_insn "*avx512f_scatterdi<mode>"
> +(define_insn "*avx512f_scatterdi<VI48F:mode>"
> [(set (match_operator:VI48F 5 "vsib_mem_operator"
> [(unspec:P
> [(match_operand:P 0 "vsib_address_operand" "Tv")
