This patch is part of a series that fixes ambiguous attribute
uses in .md files, i.e. cases in which attributes didn't use
<ITER:ATTR> to specify an iterator, and in which <ATTR> could
have different values depending on the iterator chosen.
I think this is a genuine bugfix for the case in which the 1REG_MODE
and 1REG_ALT are different, since previously we would use the 1REG_MODE
for both the comparison and the select, even though the operands being
compared are 1REG_ALT rather than 1REG_MODE.
2019-07-05 Richard Sandiford <richard.sandif...@arm.com>
gcc/
* config/gcn/gcn-valu.md
(vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>): Use
gen_vec_cmp<VEC_1REG_ALT:mode>di rather than (implicitly)
gen_vec_cmp<VEC_1REG_MODE:mode>di. Explicitly use
gen_vcond_mask_<VEC_1REG_MODE:mode>di.
(vcond<VEC_1REG_MODE:mode><VEC_1REG_ALT:mode>_exec): Likewise,
but using the _exec comparison patterns.
(vcondu<VEC_1REG_INT_MODE:mode><VEC_1REG_INT_ALT:mode>): Use
gen_vec_cmp<VEC_1REG_INT_ALT:mode>di rather than (implicitly)
gen_vec_cmp<VEC_1REG_INT_MODE:mode>di. Explicitly use
gen_vcond_mask_<VEC_1REG_INT_MODE:mode>di.
(vcondu<VEC_1REG_INT_MODE:mode><VEC_1REG_INT_ALT:mode>_exec): Likewise,
but using the _exec comparison patterns.
Index: gcc/config/gcn/gcn-valu.md
===================================================================
--- gcc/config/gcn/gcn-valu.md 2019-03-08 18:15:37.764736305 +0000
+++ gcc/config/gcn/gcn-valu.md 2019-07-05 15:05:24.076486317 +0100
@@ -2574,10 +2574,10 @@ (define_expand "vcond<VEC_1REG_MODE:mode
""
{
rtx tmp = gen_reg_rtx (DImode);
- emit_insn (gen_vec_cmp<mode>di (tmp, operands[3], operands[4],
- operands[5]));
- emit_insn (gen_vcond_mask_<mode>di (operands[0], operands[1], operands[2],
- tmp));
+ emit_insn (gen_vec_cmp<VEC_1REG_ALT:mode>di
+ (tmp, operands[3], operands[4], operands[5]));
+ emit_insn (gen_vcond_mask_<VEC_1REG_MODE:mode>di
+ (operands[0], operands[1], operands[2], tmp));
DONE;
})
@@ -2592,10 +2592,10 @@ (define_expand "vcond<VEC_1REG_MODE:mode
""
{
rtx tmp = gen_reg_rtx (DImode);
- emit_insn (gen_vec_cmp<mode>di_exec (tmp, operands[3], operands[4],
- operands[5], operands[6]));
- emit_insn (gen_vcond_mask_<mode>di (operands[0], operands[1], operands[2],
- tmp));
+ emit_insn (gen_vec_cmp<VEC_1REG_ALT:mode>di_exec
+ (tmp, operands[3], operands[4], operands[5], operands[6]));
+ emit_insn (gen_vcond_mask_<VEC_1REG_MODE:mode>di
+ (operands[0], operands[1], operands[2], tmp));
DONE;
})
@@ -2609,10 +2609,10 @@ (define_expand "vcondu<VEC_1REG_INT_MODE
""
{
rtx tmp = gen_reg_rtx (DImode);
- emit_insn (gen_vec_cmp<mode>di (tmp, operands[3], operands[4],
- operands[5]));
- emit_insn (gen_vcond_mask_<mode>di (operands[0], operands[1], operands[2],
- tmp));
+ emit_insn (gen_vec_cmp<VEC_1REG_INT_ALT:mode>di
+ (tmp, operands[3], operands[4], operands[5]));
+ emit_insn (gen_vcond_mask_<VEC_1REG_INT_MODE:mode>di
+ (operands[0], operands[1], operands[2], tmp));
DONE;
})
@@ -2627,10 +2627,10 @@ (define_expand "vcondu<VEC_1REG_INT_MODE
""
{
rtx tmp = gen_reg_rtx (DImode);
- emit_insn (gen_vec_cmp<mode>di_exec (tmp, operands[3], operands[4],
- operands[5], operands[6]));
- emit_insn (gen_vcond_mask_<mode>di (operands[0], operands[1], operands[2],
- tmp));
+ emit_insn (gen_vec_cmp<VEC_1REG_INT_ALT:mode>di_exec
+ (tmp, operands[3], operands[4], operands[5], operands[6]));
+ emit_insn (gen_vcond_mask_<VEC_1REG_INT_MODE:mode>di
+ (operands[0], operands[1], operands[2], tmp));
DONE;
})
