Prathamesh Kulkarni <prathamesh.kulka...@linaro.org> writes:
> 2019-06-07 Prathamesh Kulkarni <prathamesh.kulka...@linaro.org>
>
> * gcc.target/aarch64/sve/init_1.c: Remove options
> -O2 -fno-schedule-insns and instead pass -O.
> Update assembly in comments.
> * gcc.target/aarch64/sve/init_2.c: Likewise.
> * gcc.target/aarch64/sve/init_3.c: Likewise.
> * gcc.target/aarch64/sve/init_4.c: Likewise.
> * gcc.target/aarch64/sve/init_5.c: Likewise and additionally
> adjust dg-scan.
> * gcc.target/aarch64/sve/init_6.c: Likewise.
> * gcc.target/aarch64/sve/init_7.c: Likewise.
> * gcc.target/aarch64/sve/init_8.c: Likewise.
> * gcc.target/aarch64/sve/init_9.c: Likewise.
> * gcc.target/aarch64/sve/init_10.c: Likewise.
> * gcc.target/aarch64/sve/init_11.c: Likewise.
> * gcc.target/aarch64/sve/init_12.c: Likewise.
>
> diff --git a/gcc/testsuite/gcc.target/aarch64/sve/init_1.c
> b/gcc/testsuite/gcc.target/aarch64/sve/init_1.c
> index 5c14b603f46..4f18088f3b0 100644
> --- a/gcc/testsuite/gcc.target/aarch64/sve/init_1.c
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/init_1.c
> @@ -1,5 +1,5 @@
> /* { dg-do assemble { target aarch64_asm_sve_ok } } */
> -/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps"
> } */
> +/* { dg-options "-O -msve-vector-bits=256 --save-temps" } */
>
> /* Case 1.1: Trailing constants with stepped sequence. */
>
> @@ -17,10 +17,10 @@ vnx4si foo(int a, int b)
> foo:
> .LFB0:
> .cfi_startproc
> - ptrue p0.s, vl8
> index z0.s, #1, #1
> insr z0.s, w1
> insr z0.s, w0
> + ptrue p0.s, vl8
> ret
> */
Let's drop the ptrues as well, since they only exist to feed the
st1ws and are rightly not part of the matched code. (Same for all
tests that have a ptrue at the end.)
OK with that change, thanks.
Richard
