On 03/06/2019 08:26, Prathamesh Kulkarni wrote:
> +++ b/gcc/testsuite/gcc.target/aarch64/sve/init_8.c
> @@ -0,0 +1,32 @@
> +/* { dg-do assemble { target aarch64_asm_sve_ok } } */
> +/* { dg-options "-O2 -fno-schedule-insns -msve-vector-bits=256 --save-temps"
> } */
> +
> +/* Case 5.2: Interleaved elements and constants. */
> +
> +#include <stdint.h>
> +
> +typedef int32_t vnx4si __attribute__((vector_size (32)));
> +
> +__attribute__((noipa))
> +vnx4si foo(int a, int b, int c, int d)
> +{
> + return (vnx4si) { a, 1, b, 2, c, 3, d, 4 };
> +}
> +
> +/*
> +foo:
> +.LFB0:
> + .cfi_startproc
> + ptrue p0.s, vl8
> + mov z0.s, w3
> + adrp x3, .LANCHOR0
> + insr z0.s, w2
> + add x3, x3, :lo12:.LANCHOR0
> + insr z0.s, w1
> + ld1w z1.s, p0/z, [x3]
> + insr z0.s, w0
> + zip1 z0.s, z0.s, z1.s
> + ret
> +*/
> +
> +/* { dg-final { scan-assembler {\tmov\t(z[0-9]+\.s), w3\n\tadrp\t(x[0-9]+),
> \.LANCHOR0\n\tinsr\t\1, w2\n\tadd\t\2, \2, :lo12:\.LANCHOR0\n\tinsr\t\1,
> w1\n\tld1w\t(z[0-9]+\.s), p[0-9]+/z, \[\2\]\n\tinsr\t\1, w0\n\tzip1\t\1, \1,
> \3} } } */
this fails with tiny model when i'm testing aarch64-none-elf
$ make check-c 'RUNTESTFLAGS=--target_board=aarch64-elf-qemu{-mcmodel=tiny}
aarch64-sve.exp=init_8.c'
...
FAIL: gcc.target/aarch64/sve/init_8.c -march=armv8.2-a+sve scan-assembler
\\tmov\\t(z[0-9]+\\.s), w3\\n\\tadrp\\t(x[0-9]+),
\\.LANCHOR0\\n\\tinsr\\t\\1, w2\\n\\tadd\\t\\2, \\2,
:lo12:\\.LANCHOR0\\n\\tinsr\\t\\1, w1\\n\\tld1w\\t(z[0-9]+\\.s), p[0-9]+/z,
\\[\\2\\]\\n\\tinsr\\t\\1, w0\\n\\tzip1\\t\\1, \\1, \\3
i think you need conditional scan asm for { target aarch64_small }
and { target aarch64_tiny } or just skip the test for tiny, but
even then matching exact register name and instruction scheduling
seems fragile.
tiny code:
.arch armv8.2-a+crc+sve
.file "init_8.c"
.text
.align 2
.p2align 3,,7
.global foo
.type foo, %function
foo:
ptrue p0.s, vl8
adr x4, .LC0
mov z0.s, w3
ld1w z1.s, p0/z, [x4]
insr z0.s, w2
insr z0.s, w1
insr z0.s, w0
zip1 z0.s, z0.s, z1.s
st1w z0.s, p0, [x8]
ret
.size foo, .-foo
.align 4
.LC0:
.word 1
.word 2
.word 3
.word 4
.word 3
.word 4
.word 3
.word 4
