Hi,
This patch introduces the infrastructure to support -mcpu=future, used for
features
in a future architecture, as yet unnamed. Reworked to incorporate comments from
Segher and Alan. Thanks for the reviews!
Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no regressions.
Is
this okay for trunk?
Thanks,
Bill
Add infrastructure to support -mcpu=future to represent a future
architecture level, as yet unnamed.
[gcc]
2019-05-23 Bill Schmidt <wschm...@linux.ibm.com>
Michael Meissner <meiss...@linux.ibm.com>
Segher Boessenkool <seg...@kernel.crashing.org>
* config.gcc: Add future cpu.
* config/rs6000/driver-rs6000.c (asm_names): Add future cpu.
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New
#define.
(POWERPC_MASKS): Add OPTION_MASK_FUTURE.
(RS6000_CPU): New instantiation for future cpu.
* config/rs6000/rs6000-opts.h (enum processor_type): Add
PROCESSOR_FUTURE.
* config/rs6000/rs6000-string.c (expand_compare_loop): Treat
PROCESSOR_FUTURE like PROCESSOR_POWER9 for now.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Treat
PROCESSOR_FUTURE similarly to PROCESSOR_POWER9 for now.
(rs6000_machine_from_flags): Handle future cpu.
(rs6000_reassociation_width): Treat PROCESSOR_FUTURE like
PROCESSOR_POWER9 for now.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_mask): Add entry for future.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Add future cpu.
(MASK_FUTURE): New #define.
* config/rs6000/rs6000.md (define_attr "cpu"): Add future cpu.
* config/rs6000/rs6000.opt (mfuture): New target option.
* doc/invoke.texi (mcpu): Add future cpu.
[gcc/testsuite]
2019-05-23 Bill Schmidt <wschm...@linux.ibm.com>
* gcc.target/powerpc/cpu-future.c: New test.
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 76bb316942d..af5cd77f84c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -506,7 +506,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500|xfuture)
cpu_is_64bit=yes
;;
esac
diff --git a/gcc/config/rs6000/driver-rs6000.c
b/gcc/config/rs6000/driver-rs6000.c
index fde2a127ef1..cd6c889e368 100644
--- a/gcc/config/rs6000/driver-rs6000.c
+++ b/gcc/config/rs6000/driver-rs6000.c
@@ -457,6 +457,7 @@ static const struct asm_name asm_names[] = {
{ "630", "-m620" },
{ "970", "-m970" },
{ "G5", "-m970" },
+ { "future", "-mfuture" },
{ NULL, "\
%{mvsx: -mpwr6; \
maltivec: -m970; \
@@ -520,6 +521,7 @@ static const struct asm_name asm_names[] = {
{ "e5500", "-me5500" },
{ "e6500", "-me6500" },
{ "titan", "-mtitan" },
+ { "future", "-mfuture" },
{ NULL, "\
%{mpower9-vector: -mpower9; \
mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index d0d69beafd4..6220f2bdd59 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -72,6 +72,10 @@
| OPTION_MASK_P9_VECTOR \
| OPTION_MASK_DIRECT_MOVE)
+/* Support for a future processor's features. */
+#define ISA_FUTURE_MASKS_SERVER (ISA_3_0_MASKS_SERVER
\
+ | OPTION_MASK_FUTURE)
+
/* Flags that need to be turned off if -mno-power9-vector. */
#define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_P9_MINMAX)
@@ -112,6 +116,7 @@
| OPTION_MASK_FLOAT128_HW \
| OPTION_MASK_FLOAT128_KEYWORD \
| OPTION_MASK_FPRND \
+ | OPTION_MASK_FUTURE \
| OPTION_MASK_HTM \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF \
@@ -227,3 +232,5 @@ RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, MASK_PPC_GFXOPT | MASK_POWERPC64)
RS6000_CPU ("powerpc64le", PROCESSOR_POWER8, MASK_POWERPC64 |
ISA_2_7_MASKS_SERVER)
RS6000_CPU ("rs64", PROCESSOR_RS64A, MASK_PPC_GFXOPT | MASK_POWERPC64)
+RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64
+ | ISA_FUTURE_MASKS_SERVER)
diff --git a/gcc/config/rs6000/rs6000-opts.h b/gcc/config/rs6000/rs6000-opts.h
index 6adbf80b334..ae877bc550c 100644
--- a/gcc/config/rs6000/rs6000-opts.h
+++ b/gcc/config/rs6000/rs6000-opts.h
@@ -62,6 +62,8 @@ enum processor_type
PROCESSOR_POWER8,
PROCESSOR_POWER9,
+ PROCESSOR_FUTURE,
+
PROCESSOR_RS64A,
PROCESSOR_MPCCORE,
PROCESSOR_CELL,
diff --git a/gcc/config/rs6000/rs6000-string.c
b/gcc/config/rs6000/rs6000-string.c
index 560ecbaccc7..b9391855e16 100644
--- a/gcc/config/rs6000/rs6000-string.c
+++ b/gcc/config/rs6000/rs6000-string.c
@@ -963,6 +963,7 @@ expand_compare_loop (rtx operands[])
max_bytes = 64;
break;
case PROCESSOR_POWER9:
+ case PROCESSOR_FUTURE:
if (bytes_is_const)
max_bytes = 191;
else
diff --git a/gcc/config/rs6000/rs6000-tables.opt
b/gcc/config/rs6000/rs6000-tables.opt
index fa2e66bfdb7..911ed0923b9 100644
--- a/gcc/config/rs6000/rs6000-tables.opt
+++ b/gcc/config/rs6000/rs6000-tables.opt
@@ -194,3 +194,6 @@ Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(54)
EnumValue
Enum(rs6000_cpu_opt_value) String(rs64) Value(55)
+EnumValue
+Enum(rs6000_cpu_opt_value) String(future) Value(56)
+
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d08ba6c2d01..8ad59ecb481 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4436,6 +4436,7 @@ rs6000_option_override_internal (bool global_init_p)
&& rs6000_tune != PROCESSOR_POWER7
&& rs6000_tune != PROCESSOR_POWER8
&& rs6000_tune != PROCESSOR_POWER9
+ && rs6000_tune != PROCESSOR_FUTURE
&& rs6000_tune != PROCESSOR_PPCA2
&& rs6000_tune != PROCESSOR_CELL
&& rs6000_tune != PROCESSOR_PPC476);
@@ -4449,6 +4450,7 @@ rs6000_option_override_internal (bool global_init_p)
|| rs6000_tune == PROCESSOR_POWER7
|| rs6000_tune == PROCESSOR_POWER8
|| rs6000_tune == PROCESSOR_POWER9
+ || rs6000_tune == PROCESSOR_FUTURE
|| rs6000_tune == PROCESSOR_PPCE500MC
|| rs6000_tune == PROCESSOR_PPCE500MC64
|| rs6000_tune == PROCESSOR_PPCE5500
@@ -4749,6 +4751,7 @@ rs6000_option_override_internal (bool global_init_p)
break;
case PROCESSOR_POWER9:
+ case PROCESSOR_FUTURE:
rs6000_cost = &power9_cost;
break;
@@ -5638,6 +5641,9 @@ static const char *rs6000_machine;
static const char *
rs6000_machine_from_flags (void)
{
+ if ((rs6000_isa_flags & (ISA_FUTURE_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER))
+ != 0)
+ return "future";
if ((rs6000_isa_flags & (ISA_3_0_MASKS_SERVER & ~ISA_2_7_MASKS_SERVER)) != 0)
return "power9";
if ((rs6000_isa_flags & (ISA_2_7_MASKS_SERVER & ~ISA_2_6_MASKS_SERVER)) != 0)
@@ -9109,6 +9115,7 @@ rs6000_reassociation_width (unsigned int opc
ATTRIBUTE_UNUSED,
{
case PROCESSOR_POWER8:
case PROCESSOR_POWER9:
+ case PROCESSOR_FUTURE:
if (DECIMAL_FLOAT_MODE_P (mode))
return 1;
if (VECTOR_MODE_P (mode))
@@ -30183,7 +30190,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type,
rtx_insn *dep_insn, int cost,
some cycles later. */
/* Separate a load from a narrower, dependent store. */
- if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9)
+ if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9
+ || rs6000_tune == PROCESSOR_FUTURE)
&& GET_CODE (PATTERN (insn)) == SET
&& GET_CODE (PATTERN (dep_insn)) == SET
&& MEM_P (XEXP (PATTERN (insn), 1))
@@ -30221,6 +30229,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type,
rtx_insn *dep_insn, int cost,
|| rs6000_tune == PROCESSOR_POWER7
|| rs6000_tune == PROCESSOR_POWER8
|| rs6000_tune == PROCESSOR_POWER9
+ || rs6000_tune == PROCESSOR_FUTURE
|| rs6000_tune == PROCESSOR_CELL)
&& recog_memoized (dep_insn)
&& (INSN_CODE (dep_insn) >= 0))
@@ -30800,6 +30809,7 @@ rs6000_issue_rate (void)
case PROCESSOR_POWER8:
return 7;
case PROCESSOR_POWER9:
+ case PROCESSOR_FUTURE:
return 6;
default:
return 1;
@@ -34652,7 +34662,8 @@ rs6000_register_move_cost (machine_mode mode,
can't be a nop, whereas with ideal register
allocation a move within the same class might turn
out to be a nop. */
- if (rs6000_tune == PROCESSOR_POWER9)
+ if (rs6000_tune == PROCESSOR_POWER9
+ || rs6000_tune == PROCESSOR_FUTURE)
ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
else
ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
@@ -36254,6 +36265,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "float128", OPTION_MASK_FLOAT128_KEYWORD, false,
true },
{ "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
{ "fprnd", OPTION_MASK_FPRND, false, true },
+ { "future", OPTION_MASK_FUTURE, false, true },
{ "hard-dfp", OPTION_MASK_DFP, false,
true },
{ "htm", OPTION_MASK_HTM, false, true },
{ "isel", OPTION_MASK_ISEL, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 98a15854b42..335d75ae85f 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -138,6 +138,7 @@
mcpu=e5500: -me5500; \
mcpu=e6500: -me6500; \
mcpu=titan: -mtitan; \
+ mcpu=future: -mfuture; \
!mcpu*: %{mpower9-vector: -mpower9; \
mpower8-vector|mcrypto|mdirect-move|mhtm: -mpower8; \
mvsx: -mpower7; \
@@ -524,6 +525,7 @@ extern int rs6000_vector_align[];
#define MASK_STRICT_ALIGN OPTION_MASK_STRICT_ALIGN
#define MASK_UPDATE OPTION_MASK_UPDATE
#define MASK_VSX OPTION_MASK_VSX
+#define MASK_FUTURE OPTION_MASK_FUTURE
#ifndef IN_LIBGCC2
#define MASK_POWERPC64 OPTION_MASK_POWERPC64
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 32c41f37127..71613e21384 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -261,7 +261,7 @@
ppc750,ppc7400,ppc7450,
ppc403,ppc405,ppc440,ppc476,
ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
- power4,power5,power6,power7,power8,power9,
+ power4,power5,power6,power7,power8,power9,future,
rs64a,mpccore,cell,ppca2,titan"
(const (symbol_ref "(enum attr_cpu) rs6000_tune")))
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index f4b5c91e11f..196e75d7009 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -569,3 +569,7 @@ long rs6000_stack_protector_guard_offset = 0
;; branches via the CTR.
mspeculate-indirect-jumps
Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save
+
+mfuture
+Target Report Mask(FUTURE) Var(rs6000_isa_flags)
+Use instructions for a future architecture.
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 5e3e8873d35..fbbc4f829b7 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -24077,8 +24077,8 @@ Supported values for @var{cpu_type} are @samp{401},
@samp{403},
@samp{e6500}, @samp{ec603e}, @samp{G3}, @samp{G4}, @samp{G5},
@samp{titan}, @samp{power3}, @samp{power4}, @samp{power5}, @samp{power5+},
@samp{power6}, @samp{power6x}, @samp{power7}, @samp{power8},
-@samp{power9}, @samp{powerpc}, @samp{powerpc64}, @samp{powerpc64le},
-@samp{rs64}, and @samp{native}.
+@samp{power9}, @samp{future}, @samp{powerpc}, @samp{powerpc64},
+@samp{powerpc64le}, @samp{rs64}, and @samp{native}.
@option{-mcpu=powerpc}, @option{-mcpu=powerpc64}, and
@option{-mcpu=powerpc64le} specify pure 32-bit PowerPC (either
diff --git a/gcc/testsuite/gcc.target/powerpc/cpu-future.c
b/gcc/testsuite/gcc.target/powerpc/cpu-future.c
new file mode 100644
index 00000000000..d0725867ffa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/cpu-future.c
@@ -0,0 +1,6 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Ensure -mcpu=future compiles cleanly. */
+
+void x (void) { }
