[PATCH] i386: Adjust gcc.target/i386/pr22076.c for 64-bit

[H.J. Lu]

With SSE emulation of MMX intrinsics in 64-bit mode,

---
__v8qi test ()
{
  __v8qi mm0 = {1,2,3,4,5,6,7,8};
  __v8qi mm1 = {11,22,33,44,55,66,77,88};
  volatile __m64 x;

  x = _mm_add_pi8 (mm0, mm1);

  return x;
}
---

is compiled into

        movq    .LC0(%rip), %xmm0
        movq    .LC1(%rip), %xmm1
        paddb   %xmm1, %xmm0
        movq    %xmm0, -8(%rsp)
        movq    -8(%rsp), %xmm0
        ret

instead of

        movq    .LC1(%rip), %mm0
        paddb   .LC0(%rip), %mm0
        movq    %mm0, -8(%rsp)
        movq    -8(%rsp), %xmm0
        ret

Adjust gcc.target/i386/pr22076.c for 64-bit.

        * gcc.target/i386/pr22076.c: Adjusted for 64-bit.
---
 gcc/testsuite/gcc.target/i386/pr22076.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/testsuite/gcc.target/i386/pr22076.c 
b/gcc/testsuite/gcc.target/i386/pr22076.c
index 6c1620b4a3b..38c29dcc35b 100644
--- a/gcc/testsuite/gcc.target/i386/pr22076.c
+++ b/gcc/testsuite/gcc.target/i386/pr22076.c
@@ -15,5 +15,6 @@ __v8qi test ()
   return x;
 }
 
-/* { dg-final { scan-assembler-times "movq" 3 } } */
+/* { dg-final { scan-assembler-times "movq" 3 { target ia32 } } } */
+/* { dg-final { scan-assembler-times "movq" 4 { target { ! ia32 } } } } */
 /* { dg-final { scan-assembler-not "movl" { target nonpic } } } */
-- 
2.20.1