From: Richard Henderson <r...@redhat.com>
Date: Sun, 06 Nov 2011 09:55:17 -0800
> On 11/05/2011 07:39 PM, David Miller wrote:
>> Richard, is there a better way to represent this in RTL? These
>> instructions basically load a single byte or half-word into the bottom
>> of a 64-bit float register, and clear the rest of that register with
>> zeros. So the v4hi one is essentially loading the vector:
>>
>> [(const_int 0) (const_int 0)
>> (const_int 0) (mem:HI (register:P ...))]
>
> Try
That works, thanks a lot Richard.
--------------------
[PATCH] Get rid of sparc's UNSPEC_SHORT_LOAD.
* config/sparc/sparc.md (UNSPEC_SHORT_LOAD): Delete.
(zero_extend_v8qi_vis, zero_extend_v4hi_vis,
*zero_extend_v8qi_<P:mode>_insn,
*zero_extend_v4hi_<P:mode>_insn): Express using vec_merge
and vec_duplicate instead of using an UNSPEC.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@181063
138bc75d-0d04-0410-961f-82ee72b054a4
---
gcc/ChangeLog | 8 ++++++++
gcc/config/sparc/sparc.md | 33 ++++++++++++++++++++++-----------
2 files changed, 30 insertions(+), 11 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index b3a5be1..59c4ffc 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2011-11-06 David S. Miller <da...@davemloft.net>
+
+ * config/sparc/sparc.md (UNSPEC_SHORT_LOAD): Delete.
+ (zero_extend_v8qi_vis, zero_extend_v4hi_vis,
+ *zero_extend_v8qi_<P:mode>_insn,
+ *zero_extend_v4hi_<P:mode>_insn): Express using vec_merge
+ and vec_duplicate instead of using an UNSPEC.
+
2011-11-07 Alan Modra <amo...@gmail.com>
PR target/30282
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 7452f96..56f4dc0 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -92,7 +92,6 @@
(UNSPEC_MUL8 86)
(UNSPEC_MUL8SU 87)
(UNSPEC_MULDSU 88)
- (UNSPEC_SHORT_LOAD 89)
])
(define_constants
@@ -7833,8 +7832,11 @@
(define_expand "zero_extend_v8qi_vis"
[(set (match_operand:V8QI 0 "register_operand" "")
- (unspec:V8QI [(match_operand:QI 1 "memory_operand" "")]
- UNSPEC_SHORT_LOAD))]
+ (vec_merge:V8QI
+ (vec_duplicate:V8QI
+ (match_operand:QI 1 "memory_operand" ""))
+ (match_dup 2)
+ (const_int 254)))]
"TARGET_VIS"
{
if (! REG_P (XEXP (operands[1], 0)))
@@ -7842,12 +7844,16 @@
rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
operands[1] = replace_equiv_address (operands[1], addr);
}
+ operands[2] = CONST0_RTX (V8QImode);
})
(define_expand "zero_extend_v4hi_vis"
[(set (match_operand:V4HI 0 "register_operand" "")
- (unspec:V4HI [(match_operand:HI 1 "memory_operand" "")]
- UNSPEC_SHORT_LOAD))]
+ (vec_merge:V4HI
+ (vec_duplicate:V4HI
+ (match_operand:HI 1 "memory_operand" ""))
+ (match_dup 2)
+ (const_int 14)))]
"TARGET_VIS"
{
if (! REG_P (XEXP (operands[1], 0)))
@@ -7855,21 +7861,26 @@
rtx addr = force_reg (Pmode, XEXP (operands[1], 0));
operands[1] = replace_equiv_address (operands[1], addr);
}
+ operands[2] = CONST0_RTX (V4HImode);
})
(define_insn "*zero_extend_v8qi_<P:mode>_insn"
[(set (match_operand:V8QI 0 "register_operand" "=e")
- (unspec:V8QI [(mem:QI
- (match_operand:P 1 "register_operand" "r"))]
- UNSPEC_SHORT_LOAD))]
+ (vec_merge:V8QI
+ (vec_duplicate:V8QI
+ (mem:QI (match_operand:P 1 "register_operand" "r")))
+ (match_operand:V8QI 2 "const_zero_operand" "Y")
+ (const_int 254)))]
"TARGET_VIS"
"ldda\t[%1] 0xd0, %0")
(define_insn "*zero_extend_v4hi_<P:mode>_insn"
[(set (match_operand:V4HI 0 "register_operand" "=e")
- (unspec:V4HI [(mem:HI
- (match_operand:P 1 "register_operand" "r"))]
- UNSPEC_SHORT_LOAD))]
+ (vec_merge:V4HI
+ (vec_duplicate:V4HI
+ (mem:HI (match_operand:P 1 "register_operand" "r")))
+ (match_operand:V4HI 2 "const_zero_operand" "Y")
+ (const_int 14)))]
"TARGET_VIS"
"ldda\t[%1] 0xd2, %0")
--
1.7.6.401.g6a319
