On 11/05/2011 07:39 PM, David Miller wrote:
> Richard, is there a better way to represent this in RTL? These
> instructions basically load a single byte or half-word into the bottom
> of a 64-bit float register, and clear the rest of that register with
> zeros. So the v4hi one is essentially loading the vector:
>
> [(const_int 0) (const_int 0)
> (const_int 0) (mem:HI (register:P ...))]
Try
(define_insn "*zero_extend_v4hi_vis"
[(set (match_operand:V4HI 0 "register_operand" "=e")
(vec_merge:V4HI
(vec_duplicate:V4HI
(match_operand:HI 1 "memory_operand" "m"))
(match_operand:V4HI 2 "const_zero_operand" "")
(const_int 14)))]
...
)
(define_expand "zero_extend_v4hi_vis"
[(set (match_operand:V4HI 0 "register_operand" "=e")
(vec_merge:V4HI
(vec_duplicate:V4HI
(match_operand:HI 1 "memory_operand" "m"))
(match_dup 2)
(const_int 14)))]
"TARGET_VIS"
{
operands[2] = CONST0_RTX (V4HImode);
})
r~
