Hi all,
The mul64 attribute in types.md causes some confusion as it is used to represent
aarch32 instructions that do widening multiplication to generate 32->64 bit
results.
But these types are shared with aarch64, which has native 64-bit multiplication
operations.
Those are currently not properly represented, which I will fix in follow-up
patches.
For now, this patch renames the mul64 attribute to widen_mul64 to more clearly
communicate its meaning.
It mechanically updates all users of that name in config/arm/ (there are no
users in config/aarch64).
There is thus no change in behaviour.
Bootstrapped and tested on arm-none-linux-gnueabihf and compile-tested on
aarch64.
Committing to trunk.
Thanks,
Kyrill
2018-11-26 Kyrylo Tkachov <kyrylo.tkac...@arm.com>
* config/arm/types.md (mul64): Rename to...
(widen_mul64): ... This.
* config/arm/arm-generic.md: Rename mul64 to widen_mul64.
* config/arm/cortex-a15.md: Likewise.
* config/arm/cortex-a5.md: Likewise.
* config/arm/cortex-a53.md: Likewise.
* config/arm/cortex-a57.md: Likewise.
* config/arm/cortex-a7.md: Likewise.
* config/arm/cortex-m4.md: Likewise.
* config/arm/exynos-m1.md: Likewise.
* config/arm/marvell-pj4.md: Likewise.
* config/arm/xgene1.md: Likewise.
diff --git a/gcc/config/arm/arm-generic.md b/gcc/config/arm/arm-generic.md
index da97303c7587f4b39042b14999a30299e3ab381d..9b8f65c4314959a228733f904f8c04bc648f4b59 100644
--- a/gcc/config/arm/arm-generic.md
+++ b/gcc/config/arm/arm-generic.md
@@ -116,7 +116,7 @@ (define_insn_reservation "mult" 16
(and (eq_attr "generic_sched" "yes")
(and (eq_attr "ldsched" "no")
(ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes"))))
+ (eq_attr "widen_mul64" "yes"))))
"core*16")
(define_insn_reservation "mult_ldsched_strongarm" 3
@@ -124,7 +124,7 @@ (define_insn_reservation "mult_ldsched_strongarm" 3
(and (eq_attr "ldsched" "yes")
(and (eq_attr "tune" "strongarm")
(ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes")))))
+ (eq_attr "widen_mul64" "yes")))))
"core*2")
(define_insn_reservation "mult_ldsched" 4
@@ -132,7 +132,7 @@ (define_insn_reservation "mult_ldsched" 4
(and (eq_attr "ldsched" "yes")
(and (eq_attr "tune" "!strongarm")
(ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes")))))
+ (eq_attr "widen_mul64" "yes")))))
"core*4")
(define_insn_reservation "multi_cycle" 32
@@ -141,7 +141,7 @@ (define_insn_reservation "multi_cycle" 32
(and (eq_attr "type" "!load_byte,load_4,load_8,load_12,load_16,\
store_4,store_8,store_12,store_16")
(not (ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes"))))))
+ (eq_attr "widen_mul64" "yes"))))))
"core*32")
(define_insn_reservation "single_cycle" 1
diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md
index eb923ff18c6e51107492d8278cb8aeaccfaed805..9bec99ae7637e48c562bf5972263074da11f102a 100644
--- a/gcc/config/arm/cortex-a15.md
+++ b/gcc/config/arm/cortex-a15.md
@@ -105,7 +105,7 @@ (define_insn_reservation "cortex_a15_mult32" 3
;; 64-bit multiplies
(define_insn_reservation "cortex_a15_mult64" 4
(and (eq_attr "tune" "cortexa15")
- (eq_attr "mul64" "yes"))
+ (eq_attr "widen_mul64" "yes"))
"ca15_issue1,ca15_mx*2")
;; Integer divide
diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md
index 8e1fea5f969e6d56b5010b3570404d10959bc9ed..9ff98a236b7474af59cc18194fc324d8d9c39433 100644
--- a/gcc/config/arm/cortex-a5.md
+++ b/gcc/config/arm/cortex-a5.md
@@ -93,7 +93,7 @@ (define_bypass 1 "cortex_a5_alu,cortex_a5_alu_shift"
(define_insn_reservation "cortex_a5_mul" 2
(and (eq_attr "tune" "cortexa5")
(ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes")))
+ (eq_attr "widen_mul64" "yes")))
"cortex_a5_ex1")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
index d150ed20aed083edb0def9d06fe2ad85f0d658da..5e9fa88c4a15c0c8d9f0e54e9f0c740317234467 100644
--- a/gcc/config/arm/cortex-a53.md
+++ b/gcc/config/arm/cortex-a53.md
@@ -111,7 +111,7 @@ (define_insn_reservation "cortex_a53_alu_extr" 3
(define_insn_reservation "cortex_a53_mul" 4
(and (eq_attr "tune" "cortexa53")
(ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes")))
+ (eq_attr "widen_mul64" "yes")))
"cortex_a53_slot_any+cortex_a53_imul")
;; From the perspective of the GCC scheduling state machine, if we wish to
diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
index a029aeb5fa46e46fec8d3f1b914c207aacbe3a53..89e322cc248c239b00b1328f2e0fc9d59dccc298 100644
--- a/gcc/config/arm/cortex-a57.md
+++ b/gcc/config/arm/cortex-a57.md
@@ -328,7 +328,7 @@ (define_insn_reservation "cortex_a57_alu_shift_reg" 3
(define_insn_reservation "cortex_a57_mult32" 3
(and (eq_attr "tune" "cortexa57")
(ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes")))
+ (eq_attr "widen_mul64" "yes")))
"ca57_mx")
;; Integer divide
diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md
index 1765aeaf900aa74178d0c3b3677b71aa88f8a0d4..fee25161a9ea9d0789b84400f66287e71454a4db 100644
--- a/gcc/config/arm/cortex-a7.md
+++ b/gcc/config/arm/cortex-a7.md
@@ -171,7 +171,7 @@ (define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift"
(define_insn_reservation "cortex_a7_mul" 2
(and (eq_attr "tune" "cortexa7")
(ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes")))
+ (eq_attr "widen_mul64" "yes")))
"cortex_a7_both")
;; Forward the result of a multiply operation to the accumulator
diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md
index d2b2c69463612bbe8e9219816c5ee0cb9ad6be67..419f094999e53b4f4f415b7935a6807e94be78b9 100644
--- a/gcc/config/arm/cortex-m4.md
+++ b/gcc/config/arm/cortex-m4.md
@@ -44,7 +44,7 @@ (define_insn_reservation "cortex_m4_alu" 1
mvn_imm,mvn_reg,mvn_shift,mvn_shift_reg,\
mrs,multiple,no_insn")
(ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes"))))
+ (eq_attr "widen_mul64" "yes"))))
"cortex_m4_ex")
;; Byte, half-word and word load is two cycles.
diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md
index e8f962f18757dd67f28cf415113a95742ed41cae..2bdfd187ea8a5185e7d4e4511a9bafef1d043fe8 100644
--- a/gcc/config/arm/exynos-m1.md
+++ b/gcc/config/arm/exynos-m1.md
@@ -417,7 +417,7 @@ (define_insn_reservation "exynos_m1_mla" 3
(define_insn_reservation "exynos_m1_mlal" 4
(and (eq_attr "tune" "exynosm1")
- (eq_attr "mul64" "yes"))
+ (eq_attr "widen_mul64" "yes"))
"em1_alu, em1_c")
;; Integer divide
diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md
index 143a21e96ae1860f130d5cf917f1178a781bcfa6..0e24a9abd09031d3b14aa8e804dd0b03d45a51e3 100644
--- a/gcc/config/arm/marvell-pj4.md
+++ b/gcc/config/arm/marvell-pj4.md
@@ -119,8 +119,8 @@ (define_bypass 2 "pj4_alu_shift,pj4_shift"
(define_insn_reservation "pj4_ir_mul" 3
(and (eq_attr "tune" "marvell_pj4")
(ior (eq_attr "mul32" "yes")
- (eq_attr "mul64" "yes")))
- "pj4_is,pj4_mul,nothing*2,pj4_cp")
+ (eq_attr "widen_mul64" "yes")))
+ "pj4_is,pj4_mul,nothing*2,pj4_cp")
(define_insn_reservation "pj4_ir_div" 20
(and (eq_attr "tune" "marvell_pj4")
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index 055cb3e7d9414b461a9cf8da2e63f22025c2c901..3f10367545cc9b9b4f54340dcd9873df5b6ca95b 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -1100,8 +1100,8 @@ (define_attr "mul32" "no,yes"
(const_string "yes")
(const_string "no")))
-; Is this an (integer side) multiply with a 64-bit result?
-(define_attr "mul64" "no,yes"
+; Is this an (integer side) widening multiply with a 64-bit result?
+(define_attr "widen_mul64" "no,yes"
(if_then_else
(eq_attr "type"
"smlalxy,umull,umulls,umaal,umlal,umlals,smull,smulls,smlal,smlals")
diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md
index b7bec62a406e7bbf915a8930ebf2d3ab151ff549..893cb37e4bb93687de08b4d2b63848f9432b1252 100644
--- a/gcc/config/arm/xgene1.md
+++ b/gcc/config/arm/xgene1.md
@@ -169,9 +169,9 @@ (define_insn_reservation "xgene1_mul32" 4
(eq_attr "mul32" "yes"))
"xgene1_decode2op, xgene1_IXB + xgene1_multiply, xgene1_multiply, nothing, xgene1_IXB_compl")
-(define_insn_reservation "xgene1_mul64" 5
+(define_insn_reservation "xgene1_widen_mul64" 5
(and (eq_attr "tune" "xgene1")
- (eq_attr "mul64" "yes"))
+ (eq_attr "widen_mul64" "yes"))
"xgene1_decode2op, xgene1_IXB + xgene1_multiply, xgene1_multiply, nothing*2, xgene1_IXB_compl")
(define_insn_reservation "xgene1_div" 34
