Hi all, The patch adds a check if the gap is compile-time constant.
This happens when dse decides to replace the load with previous store value. The problem is that, shift sequence could not accept compile-time non-constant mode operand. Another issue raised from this issue is the inefficient code-generation for general data manipulation over mask/predicate register. In sve, some general data processing instructions don't apply on predicate registers directly. In the worst(this) case, memory load/store is generated to reload the value into a general purpose register for further data processing. We need to improve that. aarch64 sve test Okay, Okay to commit? Regards, Renlin gcc/ChangeLog: 2018-10-31 Renlin Li <renlin...@arm.com> PR target/87815 * dse.c (get_stored_val): Add check for compile-time constantness of gap. gcc/testsuite/ChangeLog: 2018-10-31 Renlin Li <renlin...@arm.com> PR target/87815 * gcc.target/aarch64/sve/pr87815.c: New.
diff --git a/gcc/dse.c b/gcc/dse.c index cfebfa0e110be56f17337dcb152984d782528889..21d166d92fcc2c2a4dd6d04bb7a7247b79b81a62 100644 --- a/gcc/dse.c +++ b/gcc/dse.c @@ -1841,7 +1841,7 @@ get_stored_val (store_info *store_info, machine_mode read_mode, else gap = read_offset - store_info->offset; - if (maybe_ne (gap, 0)) + if (gap.is_constant () && maybe_ne (gap, 0)) { poly_int64 shift = gap * BITS_PER_UNIT; poly_int64 access_size = GET_MODE_SIZE (read_mode) + gap; diff --git a/gcc/testsuite/gcc.target/aarch64/sve/pr87815.c b/gcc/testsuite/gcc.target/aarch64/sve/pr87815.c new file mode 100644 index 0000000000000000000000000000000000000000..628cedb2acce82a86b61944eb6184d7fdbb2d656 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve/pr87815.c @@ -0,0 +1,13 @@ +/* { dg-do compile { target aarch64_asm_sve_ok } } */ +/* { dg-options "-O3" } */ +int a, b, d; +short e; + +void f () +{ + for (int i = 0; i < 8; i++) + { + e = b >= 2 ?: a >> b; + d = e && b; + } +}