Hi again,
On Tue, Sep 11, 2018 at 10:04:45AM -0500, Will Schmidt wrote:
> On Fri, 2018-09-07 at 16:54 -0500, Segher Boessenkool wrote:
> > On Fri, Sep 07, 2018 at 04:27:34PM -0500, Will Schmidt wrote:
> > > -/* { dg-final { scan-assembler-times "lvx" 4 } } */
> > > -/* { dg-final { scan-assembler-times "stvx" 4 } } */
> > > -/* { dg-final { scan-assembler-times "xxpermdi" 0 } } */
> > > +/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M} 4 } } */
> > > +/* { dg-final { scan-assembler-times {\mstvx\M|\mstxvd2x\M} 4 } } */
> >
> > So you get xxpermdi when {l,st}xvd2x is generated? What platform is that
> > on? Is that the correct code to generate, or is this a regression? Is
> > this the difference between LE and BE code generation? So many questions,
> > I am sorry :-)
>
> Hi,
> No prob, thanks for the question. :-)
>
> The -v2 test is new-ish, I added it when the gimple-folding for the
> vec_xst,vec_xl intrinsics went in since i was seeing some codegen
> variations at the time. The check for the lvx,stvx instructions is
> valid IF the test is built for a power9 target. The test actually
> specifies -mcpu=power8 in it's options, so it needs to handle the lxvd2x
> +xxpermdi and xxpermdi+stxvd2 instruction pairs as appropriate for that
> processor.
lvx is the old AltiVec instruction, that uses (A+B)&-16 as address
for lvx D,A,B . The instruction new on power9 is lxv, which does
reg+imm (instead of reg+reg) addressing.
Maybe the expected result should be separated between BE and LE, or
similar.
Segher
