On Fri, 2018-09-07 at 16:54 -0500, Segher Boessenkool wrote:
> Hi!
>
> On Fri, Sep 07, 2018 at 04:27:34PM -0500, Will Schmidt wrote:
> > The expected instructions for this test (p8-vec-xl-*) were incorrect for
> > some
> > of the power targets. Add codegen variations as appropriate for
> > the targeted platform.
>
> > pr86952/testsuite
>
> I think you need to write this as PR (i.e. caps) followed by a space,
> and the component of this bug is "target" in bugzilla (which is better
> here), and the number is 86592. So:
>
> PR target/86592
>
> and it will automagically add a comment to the right bug :-)
aah, yes, my bad. thanks.
>
> > -/* { dg-final { scan-assembler-times "lvx" 4 } } */
> > -/* { dg-final { scan-assembler-times "stvx" 4 } } */
> > -/* { dg-final { scan-assembler-times "xxpermdi" 0 } } */
> > +/* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M} 4 } } */
> > +/* { dg-final { scan-assembler-times {\mstvx\M|\mstxvd2x\M} 4 } } */
>
> So you get xxpermdi when {l,st}xvd2x is generated? What platform is that
> on? Is that the correct code to generate, or is this a regression? Is
> this the difference between LE and BE code generation? So many questions,
> I am sorry :-)
Hi,
No prob, thanks for the question. :-)
The -v2 test is new-ish, I added it when the gimple-folding for the
vec_xst,vec_xl intrinsics went in since i was seeing some codegen
variations at the time. The check for the lvx,stvx instructions is
valid IF the test is built for a power9 target. The test actually
specifies -mcpu=power8 in it's options, so it needs to handle the lxvd2x
+xxpermdi and xxpermdi+stxvd2 instruction pairs as appropriate for that
processor.
> Segher
>
