Hi!
On Thu, Jun 14, 2018 at 08:12:31AM -0700, Carl Love wrote:
> --- a/gcc/testsuite/gcc.target/powerpc/altivec-7.c
> +++ b/gcc/testsuite/gcc.target/powerpc/altivec-7.c
> @@ -85,17 +85,22 @@ int main ()
> /* { dg-final { scan-assembler-times "vpkpx" 2 } } */
> /* { dg-final { scan-assembler-times "vmulesb" 1 } } */
> /* { dg-final { scan-assembler-times "vmulosb" 1 } } */
> -/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 42 { target le } }
> } */
> -/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 4 { target be } }
> } */
> +/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 42 { target { le
> && !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 4 { target { be &&
> !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times {\mlxvd2x\M|\mlxv\M} 0 { target {
> powerpc*-*-aix* } } } } */
AIX is always BE so you don't need the addition on the "le" line.
> --- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c
> +++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
> @@ -333,8 +333,9 @@ int main ()
> /* { dg-final { scan-assembler-times "xxmrglw" 8 } } */
> /* { dg-final { scan-assembler-times "vmrglh" 8 } } */
> /* { dg-final { scan-assembler-times "xxlnor" 6 } } */
> -/* { dg-final { scan-assembler-times "xxlor" 11 { target { ilp32 } } } } */
> -/* { dg-final { scan-assembler-times "xxlor" 7 { target { lp64 } } } } */
> +/* { dg-final { scan-assembler-times "xxlor" 11 { target { ilp32 &&
> !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times "xxlor" 7 { target { lp64 &&
> !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times "xxlor" 7 { target { powerpc*-*-aix* }
> } } } */
I don't know what the correct count is for 64-bit AIX; I don't think it
is the same as with 32-bit AIX.
> /* { dg-final { scan-assembler-times "vpksdus" 2 } } */
> /* { dg-final { scan-assembler-times "vperm" 4 } } */
> /* { dg-final { scan-assembler-times "xvrdpi" 2 } } */
> @@ -343,8 +344,10 @@ int main ()
> /* { dg-final { scan-assembler-times "divd" 8 { target lp64 } } } */
> /* { dg-final { scan-assembler-times "divdu" 2 { target lp64 } } } */
> /* { dg-final { scan-assembler-times "mulld" 4 { target lp64 } } } */
> -/* { dg-final { scan-assembler-times "bl __divdi3" 3 { target ilp32 } } } */
> -/* { dg-final { scan-assembler-times "bl __udivdi3" 3 { target ilp32 } } }
> */
> +/* { dg-final { scan-assembler-times "bl __divdi3" 3 { target ilp32 &&
> !powerpc*-*-\
> +aix* } } } */
I don't think continuation lines work for this. It is fine to have longer
lines for dejagnu stuff.
> -/* { dg-final { scan-assembler-times "vsl" 45 { target le } } } */
> -/* { dg-final { scan-assembler-times "vsl" 45 { target { be && ilp32 } }
> } } */
> -/* { dg-final { scan-assembler-times "vsl" 59 { target { be && lp64 } }
> } } */
> +/* { dg-final { scan-assembler-times "vsl" 45 { target { le &&
> !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times "vsl" 45 { target { { be && ilp32 }
> && !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times "vsl" 59 { target { { be && lp64 }
> && !powerpc*-*-aix* } } } } */
> +/* { dg-final { scan-assembler-times "vsl" 80 { target { powerpc*-*-aix*
> } } } } */
"vsl" will also pick up all "vslo", "vslv", "vsldoi" and whatnot. Use \m
and \M ?
So the main problem here is these testcases are compiled with -O0 (and
they have to be, most of this is optimised away otherwise). But at -O0
there is a whole bunch of register moves, which are xxlor for VSX registers.
Like a comment used to say:
/* We generate xxlor instructions for many reasons other than or'ing vector
operands or calling __builtin_vec_or(), which means we cannot rely on
their usage counts being stable. Therefore, we just ensure at least one
xxlor instruction was generated. */
/* { dg-final { scan-assembler "xxlor" } } */
and in another test we had:
/* { dg-final { scan-assembler-times {(?n)\mxxlor\M.*\mboolv4si3_internal\M} 6
} } */
(that needs -dp btw.)
Neither is pretty, but we cannot do better (or I don't see how); there is
no "xxmr" extended mnemonic for VSX register moves so we cannot see the
difference between register moves and IOR insns easily.
Segher
