On 3/16/18 5:51 PM, Segher Boessenkool wrote:
> But fctiw is an ISA 1.xx instruction already (and fctid is as well,
> but explicitly undefined for 32-bit implementations until some 2.xx,
> I forgot which, 2.02 I think?)
>
> Requiring power8 for it is weird and surprising. power8-vector doubly so.
Completely agree.
> (The issue is that pre-power8 we do not allow SImode in FPR registers.
> Which makes the current fctiw implementation fail).
A similar issue was true of SDmode, in that we couldn't save/restore
SDmode values out of FP regs without corrupting them. I can say I
didn't like the solution we were forced to use. :-(
> I think we have two good options:
>
> 1) Remove these builtins;
> or
> 2) Make them work.
Agreed. If we make them work, then the pattern that was added in revision
253238 should be fixed. The type of the source operand is defined as DFmode,
but the pattern is named as a SFmode to SImode conversion.
(define_insn "lrintsfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=d")
(unspec:SI [(match_operand:DF 1 "gpc_reg_operand" "d")]
UNSPEC_FCTIW))]
"TARGET_SF_FPR && TARGET_FPRND"
"fctiw %0,%1"
[(set_attr "type" "fp")])
Peter
