Hi!
These insns don't really need AVX512BW in any way themselves, only their
masked variants might need it for reloading of the mask register, but that
should be covered in builtins.def, doesn't need duplication in sse.md.
For non-masked it causes ICEs, because the builtins properly aren't guarded
with AVX512BW, but the insns incorrectly require that.
Fixed thusly, bootstrapped/regtested on x86_64-linux and i686-linux, ok for
trunk?
2017-12-28 Jakub Jelinek <ja...@redhat.com>
PR target/83604
* config/i386/sse.md (VI248_VLBW): Rename to ...
(VI248_AVX512VL): ... this. Don't guard V32HI with TARGET_AVX512BW.
(vpshrd_<mode><mask_name>, vpshld_<mode><mask_name>,
vpshrdv_<mode>, vpshrdv_<mode>_mask, vpshrdv_<mode>_maskz,
vpshrdv_<mode>_maskz_1, vpshldv_<mode>, vpshldv_<mode>_mask,
vpshldv_<mode>_maskz, vpshldv_<mode>_maskz_1): Use VI248_AVX512VL
mode iterator instead of VI248_VLBW.
* gcc.target/i386/pr83604.c: New test.
--- gcc/config/i386/sse.md.jj 2017-12-27 19:19:58.081660733 +0100
+++ gcc/config/i386/sse.md 2017-12-27 18:43:32.200347561 +0100
@@ -448,8 +448,8 @@ (define_mode_iterator VI124_AVX2
(define_mode_iterator VI2_AVX2_AVX512BW
[(V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI])
-(define_mode_iterator VI248_VLBW
- [(V32HI "TARGET_AVX512BW") V16SI V8DI
+(define_mode_iterator VI248_AVX512VL
+ [V32HI V16SI V8DI
(V16HI "TARGET_AVX512VL") (V8SI "TARGET_AVX512VL")
(V4DI "TARGET_AVX512VL") (V8HI "TARGET_AVX512VL")
(V4SI "TARGET_AVX512VL") (V2DI "TARGET_AVX512VL")])
@@ -20134,10 +20134,10 @@ (define_insn "vgf2p8mulb_<mode><mask_nam
(set_attr "mode" "<sseinsnmode>")])
(define_insn "vpshrd_<mode><mask_name>"
- [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
- (unspec:VI248_VLBW
- [(match_operand:VI248_VLBW 1 "register_operand" "v")
- (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm")
+ [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
+ (unspec:VI248_AVX512VL
+ [(match_operand:VI248_AVX512VL 1 "register_operand" "v")
+ (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm")
(match_operand:SI 3 "const_0_to_255_operand" "n")]
UNSPEC_VPSHRD))]
"TARGET_AVX512VBMI2"
@@ -20145,10 +20145,10 @@ (define_insn "vpshrd_<mode><mask_name>"
[(set_attr ("prefix") ("evex"))])
(define_insn "vpshld_<mode><mask_name>"
- [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
- (unspec:VI248_VLBW
- [(match_operand:VI248_VLBW 1 "register_operand" "v")
- (match_operand:VI248_VLBW 2 "nonimmediate_operand" "vm")
+ [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
+ (unspec:VI248_AVX512VL
+ [(match_operand:VI248_AVX512VL 1 "register_operand" "v")
+ (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm")
(match_operand:SI 3 "const_0_to_255_operand" "n")]
UNSPEC_VPSHLD))]
"TARGET_AVX512VBMI2"
@@ -20156,11 +20156,11 @@ (define_insn "vpshld_<mode><mask_name>"
[(set_attr ("prefix") ("evex"))])
(define_insn "vpshrdv_<mode>"
- [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
- (unspec:VI248_VLBW
- [(match_operand:VI248_VLBW 1 "register_operand" "0")
- (match_operand:VI248_VLBW 2 "register_operand" "v")
- (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
+ [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
+ (unspec:VI248_AVX512VL
+ [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
+ (match_operand:VI248_AVX512VL 2 "register_operand" "v")
+ (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
UNSPEC_VPSHRDV))]
"TARGET_AVX512VBMI2"
"vpshrdv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }"
@@ -20168,12 +20168,12 @@ (define_insn "vpshrdv_<mode>"
(set_attr "mode" "<sseinsnmode>")])
(define_insn "vpshrdv_<mode>_mask"
- [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
- (vec_merge:VI248_VLBW
- (unspec:VI248_VLBW
- [(match_operand:VI248_VLBW 1 "register_operand" "0")
- (match_operand:VI248_VLBW 2 "register_operand" "v")
- (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
+ [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VI248_AVX512VL
+ (unspec:VI248_AVX512VL
+ [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
+ (match_operand:VI248_AVX512VL 2 "register_operand" "v")
+ (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
UNSPEC_VPSHRDV)
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
@@ -20183,10 +20183,10 @@ (define_insn "vpshrdv_<mode>_mask"
(set_attr "mode" "<sseinsnmode>")])
(define_expand "vpshrdv_<mode>_maskz"
- [(match_operand:VI248_VLBW 0 "register_operand")
- (match_operand:VI248_VLBW 1 "register_operand")
- (match_operand:VI248_VLBW 2 "register_operand")
- (match_operand:VI248_VLBW 3 "nonimmediate_operand")
+ [(match_operand:VI248_AVX512VL 0 "register_operand")
+ (match_operand:VI248_AVX512VL 1 "register_operand")
+ (match_operand:VI248_AVX512VL 2 "register_operand")
+ (match_operand:VI248_AVX512VL 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512VBMI2"
{
@@ -20198,14 +20198,14 @@ (define_expand "vpshrdv_<mode>_maskz"
})
(define_insn "vpshrdv_<mode>_maskz_1"
- [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
- (vec_merge:VI248_VLBW
- (unspec:VI248_VLBW
- [(match_operand:VI248_VLBW 1 "register_operand" "0")
- (match_operand:VI248_VLBW 2 "register_operand" "v")
- (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
+ [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VI248_AVX512VL
+ (unspec:VI248_AVX512VL
+ [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
+ (match_operand:VI248_AVX512VL 2 "register_operand" "v")
+ (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
UNSPEC_VPSHRDV)
- (match_operand:VI248_VLBW 4 "const0_operand" "C")
+ (match_operand:VI248_AVX512VL 4 "const0_operand" "C")
(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
"TARGET_AVX512VBMI2"
"vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
@@ -20213,11 +20213,11 @@ (define_insn "vpshrdv_<mode>_maskz_1"
(set_attr "mode" "<sseinsnmode>")])
(define_insn "vpshldv_<mode>"
- [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
- (unspec:VI248_VLBW
- [(match_operand:VI248_VLBW 1 "register_operand" "0")
- (match_operand:VI248_VLBW 2 "register_operand" "v")
- (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
+ [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
+ (unspec:VI248_AVX512VL
+ [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
+ (match_operand:VI248_AVX512VL 2 "register_operand" "v")
+ (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
UNSPEC_VPSHLDV))]
"TARGET_AVX512VBMI2"
"vpshldv<ssemodesuffix>\t{%3, %2, %0|%0, %2, %3 }"
@@ -20225,12 +20225,12 @@ (define_insn "vpshldv_<mode>"
(set_attr "mode" "<sseinsnmode>")])
(define_insn "vpshldv_<mode>_mask"
- [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
- (vec_merge:VI248_VLBW
- (unspec:VI248_VLBW
- [(match_operand:VI248_VLBW 1 "register_operand" "0")
- (match_operand:VI248_VLBW 2 "register_operand" "v")
- (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
+ [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VI248_AVX512VL
+ (unspec:VI248_AVX512VL
+ [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
+ (match_operand:VI248_AVX512VL 2 "register_operand" "v")
+ (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
UNSPEC_VPSHLDV)
(match_dup 1)
(match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")))]
@@ -20240,10 +20240,10 @@ (define_insn "vpshldv_<mode>_mask"
(set_attr "mode" "<sseinsnmode>")])
(define_expand "vpshldv_<mode>_maskz"
- [(match_operand:VI248_VLBW 0 "register_operand")
- (match_operand:VI248_VLBW 1 "register_operand")
- (match_operand:VI248_VLBW 2 "register_operand")
- (match_operand:VI248_VLBW 3 "nonimmediate_operand")
+ [(match_operand:VI248_AVX512VL 0 "register_operand")
+ (match_operand:VI248_AVX512VL 1 "register_operand")
+ (match_operand:VI248_AVX512VL 2 "register_operand")
+ (match_operand:VI248_AVX512VL 3 "nonimmediate_operand")
(match_operand:<avx512fmaskmode> 4 "register_operand")]
"TARGET_AVX512VBMI2"
{
@@ -20255,14 +20255,14 @@ (define_expand "vpshldv_<mode>_maskz"
})
(define_insn "vpshldv_<mode>_maskz_1"
- [(set (match_operand:VI248_VLBW 0 "register_operand" "=v")
- (vec_merge:VI248_VLBW
- (unspec:VI248_VLBW
- [(match_operand:VI248_VLBW 1 "register_operand" "0")
- (match_operand:VI248_VLBW 2 "register_operand" "v")
- (match_operand:VI248_VLBW 3 "nonimmediate_operand" "vm")]
+ [(set (match_operand:VI248_AVX512VL 0 "register_operand" "=v")
+ (vec_merge:VI248_AVX512VL
+ (unspec:VI248_AVX512VL
+ [(match_operand:VI248_AVX512VL 1 "register_operand" "0")
+ (match_operand:VI248_AVX512VL 2 "register_operand" "v")
+ (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
UNSPEC_VPSHLDV)
- (match_operand:VI248_VLBW 4 "const0_operand" "C")
+ (match_operand:VI248_AVX512VL 4 "const0_operand" "C")
(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
"TARGET_AVX512VBMI2"
"vpshldv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
--- gcc/testsuite/gcc.target/i386/pr83604.c.jj 2017-12-27 19:33:19.835077783
+0100
+++ gcc/testsuite/gcc.target/i386/pr83604.c 2017-12-27 19:32:37.661052000
+0100
@@ -0,0 +1,11 @@
+/* PR target/83604 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -mno-avx" } */
+
+typedef short V __attribute__((__vector_size__(64)));
+
+__attribute__((target ("avx512vbmi2"))) V
+foo (V x, V y, V z)
+{
+ return __builtin_ia32_vpshrdv_v32hi (x, y, z);
+}
Jakub
